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參數(shù)資料
| 型號(hào)： | X9418YS24I-2.7 |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 數(shù)字電位計(jì) |
| 英文描述： | Dual Digitally Controlled Potentiometers |
| 中文描述： | DUAL 2.5K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, MS-013AD, SOIC-24 |
| 文件頁(yè)數(shù)： | 12/21頁(yè) |
| 文件大?。?/td> | 386K |
| 代理商： | X9418YS24I-2.7 |
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X9418
Characteristics subject to change without notice.
12 of 21
REV 1.1.5 7/23/02
www.xicor.com
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Notes:
(1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R
H
—R
L
)/63, single pot
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Power Up Requirements
(Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V
CC
, then V+ and V–, and then the potentiometer pins, R
H
,
R
L
, and R
W
. Voltage should not be applied to the potentiometer pins before V+ or V– is applied. The V
CC
ramp rate
specification should be met, and any glitches or slope changes in the V
CC
line should be held to <100mV if possi-
ble. If V
CC
powers down, it should be held below 0.1V for more than 1 second before powering up again in order for
proper wiper register recall. Also, V
CC
should not reverse polarity by more than 0.5V. Recall of wiper position will
not be complete until V
CC
, V+ and V– reach their final value.
Notes:
(4) This parameter is periodically sampled and not 100% tested
(5) t
PUR
and t
PUW
are the delays required from the time the third (last) power supply (V
CC
, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(6) This is a tested or guaranteed parameter and should only be used as a guidance.
Symbol
I
CC1
Parameter
Limits
Typ.
Test Conditions
f
SCL
= 400kHz, SDA = Open,
Other Inputs = V
SS
f
SCL
= 400kHz, SDA = Open,
Other Inputs = V
SS
SCL = SDA = V
CC
, Addr. = V
SS
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
Min.
Max.
1
Unit
mA
V
CC
supply current
(nonvolatile write)
V
CC
supply current
(move wiper, write, read)
V
CC
current (standby)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
I
CC2
100
μA
I
SB
I
LI
I
LO
V
IH
V
IL
V
OL
1
10
10
μA
μA
μA
V
V
V
V
CC
x 0.7
–0.5
V
CC
+ 0.5
V
CC
x 0.1
0.4
I
OL
= 3mA
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
Symbol
C
I/O
(4)
C
IN
(4)
Test
Max.
8
6
Unit
pF
pF
Test Conditions
V
I/O
= 0V
V
IN
= 0V
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3, and SCL)
Symbol
t
PUR
(5)
t
PUW
(5)
t
R
V
CC
(6)
Parameter
Min.
Typ.
Max.
1
5
50
Unit
ms
ms
V/msec
Power-up to initiation of read operation
Power-up to initiation of write operation
V
CC
Power up ramp rate
0.2
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