參數(shù)資料
型號: X9401YS24I-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Low Noise/Low Power/SPI Bus
中文描述: QUAD 2.5K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24
封裝: PLASTIC, MS-013AD, SOIC-24
文件頁數(shù): 8/20頁
文件大?。?/td> 371K
代理商: X9401YS24I-2.7
8
FN8190.2
September 23, 2005
Figure 7. Increment/Decrement Timing Limits
Table 1. Instruction Set
Instruction
Instruction Set
I
1
I
0
0
1
Operation
I
3
1
I
2
0
R
1
R
0
0
P
1
P
0
P
1
Read Wiper Counter Register
0
P
0
Read the contents of the Wiper Counter Register
pointed to by P
1
- P
0
Write new value to the Wiper Counter Register
pointed to by P
1
- P
0
Read the contents of the Data Register pointed to by
P
1
- P
0
and R
1
- R
0
Write new value to the Data Register pointed to by
P
1
- P
0
and R
1
- R
0
Transfer the contents of the Data Register pointed to
by R
1
- R
0
to the Wiper Counter Register pointed to by
P
1
- P
0
Transfer the contents of the Wiper Counter Register
pointed to by P
1
- P
0
to the Register pointed to by
R
1
- R
0
Transfer the contents of the Data Registers pointed to
by R
1
- R
0
of all four pots to their respective Wiper
Counter Register
Transfer the contents of all Wiper Counter Registers
to their respective data Registers pointed to by
R
1
- R
0
of all four pots
Enable Increment/decrement of the Wiper Counter
Register pointed to by P
1
- P
0
Read the status of the internal write cycle, by
checking the WIP bit.
Write Wiper Counter Register
1
0
1
0
0
0
P
1
P
0
Read Data Register
1
0
1
1
R
1
R
0
P
1
P
0
Write Data Register
1
1
0
0
R
1
R
0
P
1
P
0
XFR Data Register to Wiper
Counter Register
1
1
0
1
R
1
R
0
P
1
P
0
XFR Wiper Counter Register
to Data Register
1
1
1
0
R
1
R
0
P
1
P
0
Global XFR Data Register to
Wiper Counter Register
0
0
0
1
R
1
R
0
0
0
Global XFR Wiper Counter
Register to Data Register
1
0
0
0
R
1
R
0
0
0
Increment/Decrement Wiper
Counter Register
Read Status (WIP bit)
0
0
1
0
0
0
P
1
P
0
0
1
0
1
0
0
0
1
SCK
SI
V
W
/R
W
INC/DEC CMD Issued
t
WRID
Voltage Out
X9401
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