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參數(shù)資料
| 型號(hào)： | WV3EG265M72EFSU265D4IS |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, ZMA200 |
| 封裝： | SODIMM-200 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大小： | 171K |
| 代理商： | WV3EG265M72EFSU265D4IS |
WV3EG265M72EFSU-D4
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
VCC = VCCQ = +2.5V ±0.2V
AC CHARACTERISTICS
335
262
265
UNITS
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
Row cycle time
tRC
60
65
tCK
Refresh row cycle time
tRFC
72
75
ps
Row active
tRAS
42
70K
45
120K
45
120K
ps
RAS# to CAS# delay
tRCD
18
20
tCK
Row precharge time
tRP
18
20
ns
Row active to row active delay
tRRD
12
15
ns
Write recovery time
tWR
15
ns
Last data in to READ command
tWTR
111
ns
Clock cycle time
CL = 2.5
tCK (2.5)
6
12
7.5
12
7.5
12
ns
CL =2
tCK (2)
7.5
12
7.5
12
10
12
ns
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS-out access time from CK/CK#
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK#
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data stobe edge to output data edge
tDQSQ
0.45
0.5
ns
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to vaild DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
000
ns
DQS-in hold time
tWPRE
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
tCK
DQS falling edge to CK rising-hold time
tDHS
0.2
tCK
DQS-in high level width
tDQHS
0.35
tCK
DQS-in low level width
TDQSL
0.35
tCK
Address and control input setup time (fast)
tISF
0.75
0.9
ns
Address and control input hold time (fast)
tIHF
0.75
0.9
ns
Address and control input setup time (slow)
tISS
0.8
1.0
ns
Address and control input hold time (slow)
tIHS
0.8
1.0
ns
Data-out high impedance time from CK/CK#
tHZ
-0.70
+0.70
-0.75
+0.75
-0.75
+0.75
ns
Data-out low impedance time to CK/CK#
tLZ
-0.70
+0.70
-0.75
+0.75
-0.75
+0.75
ns
Mode register set cycle
tMRD
12
15
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
ns
DQ & DM hold time to DQS
tDH
0.45
0.5
ns
Control & address input pulse width
tIPW
2.2
ns
DQ & DM input pulse width
tDIPW
1.75
ns
Exit self refresh to non-read command
tXSNR
75
ns
* AC specication is based on SAMSUNG components. Other DRAM manufactures specication may be different.
Continued on next page
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG265M72EFSU265D4ISG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU265D4M | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU265D4MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU265D4N | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU265D4NG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
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