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參數(shù)資料
| 型號(hào)： | WL100PR |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | WLAN INTERFACE CIRCUIT |
| 中文描述： | 無線接口電路 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大小： | 179K |
| 代理商： | WL100PR |
MAY 1996
DS4054-2.2
The WL100, together with the DE6003 frequency hopping
radio transceiver, implements a wide variety of WLAN
applications where NRZ encoding is used.
FEATURES
I
Low Power CMOS Technology
I
Flexible Data Transceiver
I
Clock Recovery with Continuous Calibration for
Flexible Packet Length
I
Flexible Preamble Format
I
Selectable Data Rates: 156·25kb/s, 250kb/s,
312·5kb/s, 500kb/s, 625kb/s and 1Mb/s
I
CRC-32 Generator/Checker
I
Fast Antenna Diversity with Manual Override
I
Battery Level Monitoring
I
8-Bit Parallel Controller Interface
WLAN INTERFACE CIRCUIT
WL100
RELATED DOCUMENTS
DE6003 data sheet, DS3506
GPS application notes AN142,143,144,145, 154 and 203
for further design information.
ORDERING INFORMATION
WL100/CG/FP1R
- Commercial, Quad Plastic Flatpack
Prior to completion of full device characterisation, pre-
production parts will be designated
WL100/PR/FP1R.
ADVANCE INFORMATION
Fig. 1 Pin connections (top view). See Table 8 for pin
descriptions.
FP64
Fig. 2 WLAN system block diagram
PIN 1 IDENT
PIN 1
PIN 64
WL100
B
B
B
B
B
B
B
V
S
V
D
B
B
B
B
B
B
C
RD
WR
RESET
CKSEL1
CKSEL0
E_CLK
V
DD
V
SS
B_CLK
C_CLK
TEST
ATSTIN
ATSTOUT
XCKT
RXD
SYNLOK
P
P
R
T
L
S
S
V
D
V
S
C
N
S
S
S
S
S
NC
NC
IRQ
V
SS
V
SHCAP
RSSI
NC
NC
V
STDBY
V
ANTSEL
V
SS
NC
NC
WL100
WLAN INTERFACE CIRCUIT
DE6003
FREQUENCY
HOPPING
TRANSCEIVER
WLAN
MAC
CONTROLLER
HOST
MICRO-
PROCESSOR
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