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參數(shù)資料
| 型號： | W3EG6464S265D3F |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | LEAD FREE, DIMM-184 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 293K |
| 代理商： | W3EG6464S265D3F |
White Electronic Designs
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
May 2005
Rev. 3
W3EG6464S-JD3-D3
PRELIMINARY
IDD1 : OPERATING CURRENT : ONE BANK
1.
Typical Case : VCC=2.5V, T=25°C
2.
Worst Case : VCC=2.7V, T=10°C
3.
Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
4.
Timing Patterns :
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
IDD7A : OPERATING CURRENT : FOUR BANKS
1.
Typical Case : VCC=2.5V, T=25°C
2.
Worst Case : VCC=2.7V, T=10°C
3.
Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4.
Timing Patterns :
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG6464S265JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM UNBUFFERED |
| W3EG6464S335AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG6464S335BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG6464S-AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG6464S-BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM UNBUFFERED w/PLL |
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