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參數(shù)資料
| 型號： | V55C3256164VBUG10E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PBGA54 |
| 封裝： | ROHS COMPLIANT, MO-210, FBGA-54 |
| 文件頁數(shù)： | 1/46頁 |
| 文件大?。?/td> | 575K |
| 代理商： | V55C3256164VBUG10E |
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1
V55C3256164VB
256Mbit MOBILE SDRAM
3.3 VOLT FBGA PACKAGE 16M X 16
V55C3256164VB Rev. 1.0 March 2008
710
System Frequency (fCK)
143 MHz
100MHz
Clock Cycle Time (tCK3)
7 ns
10 ns
Clock Access Time (tAC3) CAS Latency = 3
5.4 ns
7 ns
Clock Access Time (tAC2) CAS Latency = 2
6 ns
8 ns
Clock Access Time (tAC1) CAS Latency = 1
19 ns
22 ns
Features
■ 4 banks x 4Mbit x 16 organization
■ High speed data transfer rates up to 143 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency:1, 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Power Down Mode and Clock Suspend Mode
■ Deep Power Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 8192 cycles/64 ms
■ Available in 54-ball FBGA, with 9x6 ball array
with 3 depupulated rows, 13x8 mm and 54 pin
TSOP II
■ Single (3.0V~3.3V)+/-0.3V Power Supply
■ Programmable Power Reduction Feature by par-
tial array activation during Self-Refresh
■ Operating Temperature Range
Commercial (0
°C to 70°C)
Industrial (-40
°C to +85°C)
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Temperature
Mark
C/T
7
10
0
°C to 70°C
Commercial
-40
°C to 85°C
Industrial
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