
User’s Manual U17553EJ4V0UD
8
CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................ 17
1.1 Features......................................................................................................................................... 17
1.2 Applications .................................................................................................................................. 18
1.3 Ordering Information ................................................................................................................... 18
1.4 Pin Configuration (Top View) ...................................................................................................... 19
1.5 Fx2 Series Lineup......................................................................................................................... 21
1.5.1 78K0/Fx2 product lineup ................................................................................................................... 21
1.6 Block Diagram .............................................................................................................................. 23
1.7 Outline of Functions .................................................................................................................... 24
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 26
2.1 Pin Function List .......................................................................................................................... 26
2.2 Description of Pin Functions ...................................................................................................... 30
2.2.1 P00, P01, P05, P06 (port 0) .............................................................................................................. 30
2.2.2 P10 to P17 (port 1) ............................................................................................................................ 31
2.2.3 P30 to P33 (port 3) ............................................................................................................................ 32
2.2.4 P40 to P47 (port 4) ............................................................................................................................ 32
2.2.5 P50 to P57 (port 5) ............................................................................................................................ 33
2.2.6 P60 to P67 (port 6) ............................................................................................................................ 33
2.2.7 P70 to P76 (port 7) ............................................................................................................................ 33
2.2.8 P80 to P87 (port 8) ............................................................................................................................ 34
2.2.9 P90 to P97 (port 9) ............................................................................................................................ 34
2.2.10 P120 to P124 (port 12) .................................................................................................................... 34
2.2.11 P130 to P132 (port 13) .................................................................................................................... 35
2.2.12 AVREF............................................................................................................................................... 36
2.2.13 AVSS ................................................................................................................................................ 36
2.2.14 RESET ............................................................................................................................................ 36
2.2.15 REGC .............................................................................................................................................. 36
2.2.16 VDD and EVDD .................................................................................................................................. 36
2.2.17 VSS and EVSS................................................................................................................................... 36
2.2.18 FLMD0 ............................................................................................................................................ 36
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 37
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 41
3.1 Memory Space .............................................................................................................................. 41
3.1.1 Internal program memory space........................................................................................................ 47
3.1.2 Bank area (
μPD78F0892 and 78F0893 only).................................................................................... 48
3.1.3 Internal data memory space .............................................................................................................. 50
3.1.4 Special function register (SFR) area ................................................................................................. 50
3.1.5 Data memory addressing .................................................................................................................. 50
3.2 Processor Registers .................................................................................................................... 54
3.2.1 Control registers ................................................................................................................................ 54
3.2.2 General-purpose registers................................................................................................................. 58
3.2.3 Special Function Registers (SFRs) ................................................................................................... 59
3.3 Instruction Address Addressing................................................................................................. 66