
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17260EJ6V0UD
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(2) Generation of serial clock
A serial clock to be generated can be specified by using baud rate generator control register 0 (BRGC0).
Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0.
Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value (fXCLK0/8 to fXCLK0/31) of the 5-bit
counter.
14.4.4 Calculation of baud rate
(1) Baud rate calculation expression
The baud rate can be calculated by the following expression.
Baud rate =
[bps]
fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register
k:
Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31)
Table 14-4. Set Value of TPS01 and TPS00
Base clock (fXCLK0) selection
Note 1
TPS01
TPS00
fPRS = 2 MHz
fPRS = 5 MHz
fPRS = 10 MHz
fPRS = 20 MHz
0
TM50 output
Note 2
0
1
fPRS/2
1 MHz
2.5 MHz
5 MHz
10 MHz
1
0
fPRS/2
3
250 kHz
625 kHz
1.25 MHz
2.5 MHz
1
fPRS/2
5
62.5 kHz
156.25 kHz
312.5 kHz
625 kHz
Notes 1. If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS ≤ 20 MHz
VDD = 2.7 to 4.0 V: fPRS ≤ 10 MHz
VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz (Standard and (A) grade products only)
2. Note the following points when selecting the TM50 output as the base clock.
Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable (TOE50 = 1) TO50 output in any mode.
(2) Error of baud rate
The baud rate error can be calculated by the following expression.
Error (%) =
1 × 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the
reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
fXCLK0
2
× k
Actual baud rate (baud rate with error)
Desired baud rate (correct baud rate)
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