
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Preliminary User’s Manual U16228EJ1V0UD
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(4) Capture register data retention timing
If the valid edge of the TI00n pin is input during 16-bit timer capture/compare register 01n (CR01n) read, CR01n
performs a capture operation. However, the value read at this time is not guaranteed.
The interrupt request flag (TMIF01n) is set upon detection of the valid edge.
Figure 6-39. Capture Register Data Retention Timing
Count clock
TM0n count value
Edge input
Interrupt request flag
Capture read signal
CR01n interrupt value
N
N + 1
N + 2
M
M + 1
M + 2
X
N + 2
Capture, but
read value is
not guaranteed
Capture
M + 1
(5) Valid edge setting
Set the valid edge of the TI00n pin after setting bits 2 and 3 (TMC0n2 and TMC0n3) of 16-bit timer mode control
register 0n (TMC0n) to 0, 0, respectively, and then stopping timer operation. The valid edge is set using bits 4
and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n).
(6) Re-triggering one-shot pulse
(a) One-shot pulse output by software
When a one-shot pulse is output, do not set the OSPT0n bit to 1. Do not output the one-shot pulse again
until INTTM00n, which occurs upon a match with the CR00n register, or INTTM01n, which occurs upon a
match with the CR01n register, occurs.
(b) One-shot pulse output with external trigger
If the external trigger occurs again while a one-shot pulse is output, it is ignored.
(c) One-shot pulse output function
When using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change
the level of the TI00n pin or its alternate function port pin.
Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the
TI00n pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing.
Remark
n = 0:
PD780131, 780132
n = 0, 1:
PD780133, 780134, 78F0134, 780136, 780138, 78F0138