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參數(shù)資料
| 型號： | UPD43256BGW-B15X-9JL |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 150 ns, PDSO28 |
| 封裝： | 8 X 13.40 MM, PLASTIC, TSOP1-28 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 269K |
| 代理商： | UPD43256BGW-B15X-9JL |
12
μPD43256B-X
Data Sheet M11012EJ7V0DS
Write Cycle Timing Chart 1 (/WE Controlled)
tWC
tCW
tWHZ
tDW
tDH
tOW
Indefinite data out
High
impe-
dance
High
impe-
dance
Data in
Indefinite data out
Address (Input)
/CS (Input)
I/O (Input / Output)
tAW
tWP
tAS
tWR
/WE (Input)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins
will remain high impedance state.
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