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參數(shù)資料
| 型號(hào)： | UPD43256BGW-B15X-9JL |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 150 ns, PDSO28 |
| 封裝： | 8 X 13.40 MM, PLASTIC, TSOP1-28 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 269K |
| 代理商： | UPD43256BGW-B15X-9JL |
11
μPD43256B-X
Data Sheet M11012EJ7V0DS
Write Cycle (1/2)
Parameter
Symbol
VCC
≥ 4.5 V
Unit
Con-
μPD43256B-70X
μPD43256B-85X
μPD43256B-AxxX
μPD43256B-BxxX
dition
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
tWC
70
85
100
ns
/CS to end of write
tCW
60
70
80
ns
Address valid to end of write
tAW
60
70
80
ns
Write pulse width
tWP
55
60
70
ns
Data valid to end of write
tDW
30
35
40
ns
Data hold time
tDH
5
ns
Address setup time
tAS
0
ns
Write recovery time
tWR
0
ns
/WE to output in high impedance
tWHZ
30
35
ns
Note
Output active from end of write
tOW
5
ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Write Cycle (2/2)
Parameter
Symbol
VCC
≥ 3.0 V
VCC
≥ 2.7 V
Unit
Con-
μPD43256B-
A85X
μPD43256B-
A10X
μPD43256B-
A12X
μPD43256B-
B10X
μPD43256B-
B15X
dition
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time
tWC
85
100
120
100
150
ns
/CS to end of write
tCW
70
90
70
100
ns
Address valid to end of write
tAW
70
90
70
100
ns
Write pulse width
tWP
60
80
60
90
ns
Data valid to end of write
tDW
60
70
60
80
ns
Data hold time
tDH
5
ns
Address setup time
tAS
0
ns
Write recovery time
tWR
0
ns
/WE to output in high impedance
tWHZ
35
40
35
40
ns
Note
Output active from end of write
tOW
5
ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
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