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參數(shù)資料
| 型號： | UPD43256BGW-B15X-9JL |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 150 ns, PDSO28 |
| 封裝： | 8 X 13.40 MM, PLASTIC, TSOP1-28 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 269K |
| 代理商： | UPD43256BGW-B15X-9JL |
9
μPD43256B-X
Data Sheet M11012EJ7V0DS
Read Cycle (1/2)
Parameter
Symbol
VCC
≥ 4.5 V
Unit
Con-
μPD43256B-70X
μPD43256B-85X
μPD43256B-AxxX
μPD43256B-BxxX
dition
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
tRC
70
85
100
ns
Address access time
tAA
70
85
100
ns
Note
/CS access time
tACS
70
85
100
ns
/OE access time
tOE
35
40
50
ns
Output hold from address change
tOH
10
ns
/CS to output in low impedance
tCLZ
10
ns
/OE to output in low impedance
tOLZ
5
ns
/CS to output in high impedance
tCHZ
30
35
ns
/OE to output in high impedance
tOHZ
30
35
ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Read Cycle (2/2)
Parameter
Symbol
VCC
≥ 3.0 V
VCC
≥ 2.7 V
Unit
Con-
μPD43256B-
A85X
μPD43256B-
A10X
μPD43256B-
A12X
μPD43256B-
B10X
μPD43256B-
B15X
dition
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time
tRC
85
100
120
100
150
ns
Address access time
tAA
85
100
120
100
150
ns
Note
/CS access time
tACS
85
100
120
100
150
ns
/OE access time
tOE
50
60
70
ns
Output hold from address change
tOH
10
ns
/CS to output in low impedance
tCLZ
10
ns
/OE to output in low impedance
tOLZ
5
ns
/CS to output in high impedance
tCHZ
35
40
35
50
ns
/OE to output in high impedance
tOHZ
35
40
35
50
ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
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