參數(shù)資料
型號(hào)： TS3843BCD
廠商： Electronic Theatre Controls, Inc.
英文描述： High Performance Current Mode Controller
中文描述： 高性能電流模式控制器
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 521K
代理商： TS3843BCD
Operating Description
The TS3842B series are high performance, fixed frequency, current mode controllers. They are
specifically designed for Off-Line and DC-to-DC converter applications offering the designer a cost
effective solution with minimal external components. A representative block diagram is shown in
Figure 17.
Oscillator
The oscillator frequency is programmed by the values selected for the timing components R
and
C
. Capacitor C
is charged from the 5.0V reference through resistor R
to approximately 2.8V
and discharge to 1.2V by an internal current sink. During the discharge of C
, the oscillator
generates an internal blanking pulse that holds the center input of the NOR gate high. This
causes the Output to be in a low state, thus producing a controlled amount of output deadtime.
Figure 1 shows R
versus Oscillator Frequency and Figure 2, Output Deadtime versus Oscillator
Frequency, both for given values of C
. Note that many values of R
and C
will give the same
oscillator frequency but only one combination will yield a specific output deadtime at a given
frequency. The oscillator thresholds are temperature compensated, and the discharge current is
trimmed and guaranteed to within ±10% at T
=25
variations of oscillator frequency and maximum output duty cycle. The results are shown in Figure
3 and 4.
. These internal circuit refines minimum
In many noise sensitive applications it may be desirable to frequency-lock the converter to an
external system clock. This can be accomplished by applying a clock signal to the circuit shown
in Figure 20 for reliable locking. The free-running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi unit synchronization is shown in Figure 21. By
tailling the clock waveform, accurate Output duty cycle clamping can be achieved.
Error Amplifier
A fully compensated Error Amplifier with access to the inverting input and output is provided. It
features a typical DC voltage gain of 90dB, and a unity gain bandwidth of 1.0MHz with 57 degrees
of phase margin (Figure 7). The non-inverting input is internally biased at 2.5V and is not pinned
out. The converter output voltage is typically divided down and monitored by the inverting input.
The maximum input bias current is -2.0
μ
A which can cause an output voltage error that is equal
to the product of the input bias current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 31). The output
voltage is offset by two diode drops (
≈
1.4V) and divided by three before it connects to the inverting
input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output
(Pin 6) when Pin 1 is at its lowest state (V
OL
). This occurs when the power supply is operating and
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