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參數(shù)資料
| 型號： | TriCore |
| 廠商： | SIEMENS AG |
| 英文描述： | 32-bit microcontrollers(32位微控制器) |
| 中文描述： | 32位微控制器（32位微控制器） |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 117K |
| 代理商： | TRICORE |
How to use the
Watchdog Timer of the TriCore
5 of 17
AP3219 Rel.02
If the Time-out Mode is not properly stopped, the WDT overflows from 0xFFFF to 0x0000
and enters the Reset Pre-warning Mode. This mode, indicated through bit
WDTSR.WDTPR=1, is similar to the Time-out Mode except that it is no longer possible to
stop the Time-Out Period.
Note:
Even when the WDT is disabled and ENDINIT is not set to 1 the Watchdog Timer is
automatically set to Time-out Mode.
Reset Pre-warning Mode is automatically triggered by the following events:
Watchdog Overflow Error (WDTSR.WDTOE=1)
Watchdog Access Error (WDTSR.WDTAE=1)
In this mode a NMI trap request to the CPU is activated. The NMISR.NMIWDT bit in the
NMI status register is set. When the Watchdog Timer again overflows from 0xFFFF to
0x0000, a reset will occur.
In this mode, a NMI trap routine can save critical system state such as the PC value, the
stack pointer, and context pointers can be stored to data memory for examination after the
reset has occurred. The Watchdog Timer also has flags that indicate the type of Watchdog
failure. This function is especially important during program debugging.
In the NMI routine, a check of the bit NMISR.NMIWDT should always be performed to
distinguish the NMI trap cause from an external NMI request.
Note:
NMIWDT has to be reset by software.
2.3
If the Watchdog Timer is used in an application and is enabled (WDTSR.WDTDS=0), it
must be regularly serviced to prevent it from overflowing.
Service is performed in two steps. First, the proper password must be written to
WDTCON0 to unlock it. Password access to WDTCON0 automatically switches the WDT
to Time-out Mode. Thus, the modifying access must be performed before the Time-out
expires or a system reset will result. During the following modifying access, the strict
requirement is that WDTCON0.ENDINIT as well as bit 1 and bits 7:4 are written with 1’s,
while bits 3:2 are written with 0’s, as shown in the chapter Modify Access.
Servicing the Watchdog Timer
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