- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385015 > TriCore (SIEMENS AG) 32-bit microcontrollers(32位微控制器) PDF資料下載
參數(shù)資料
| 型號： | TriCore |
| 廠商： | SIEMENS AG |
| 英文描述： | 32-bit microcontrollers(32位微控制器) |
| 中文描述： | 32位微控制器（32位微控制器） |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 117K |
| 代理商： | TRICORE |
How to use the
Watchdog Timer of the TriCore
4 of 17
AP3219 Rel.02
2
After a reset, the WDTCON0.ENDINIT bit is cleared, giving access to critical system
registers protected via the ENDINIT bit. WDTCON1, used to control the operation of the
Watchdog Timer, is one of the registers protected by ENDINIT.
When changing the operation of the Watchdog Timer through the controls in register
WDTCON1, these changes have no immediate effect. They go into effect only after the
ENDINIT bit has been set to 1 again. In this way, changes of these bits do not interfere
with the Time-out Operation of the WDT.
Because the WDT is in the Time-out Mode after reset, there is a time limit of 65536 system
clocks on the initialization of the critical system registers. The ENDINIT bit must be set to 1
before the Time-out expires.
WDT Initialization
2.1
After a reset, the contents of the Watchdog Timer registers are as shown in Table 2.
Default Values
Table 2
Watchdog Timer Default Values After Reset
Register
Default
Contents
Description
Reload value is 0xFFFC, WDTPW is 0; WDTCON0 is locked (WDTLCK=1);
ENDINIT is 0, so access to ENDINIT-protected registers is enabled.
WDTCON0
[31:16] 1111 1111 1111 1100
[15:0] 0000 0000 0000 0010
WDTCON1
[31:16] 0000 0000 0000 0000
[15:0] 0000 0000 0000 0000
[31:16] 1111 1111 1111 1100
[15:0] 0000 0000 0001 00xx
Watchdog Timer disable request is 0; input clock request set to fSYSCLK/16384.
WDTSR
The Watchdog counter contains 0xFFFC (the initial Time-out value); WDT is
operating in Time-out Mode (WDTTO=1); WDT is enabled (WDTDS=0); input clock
is fSYSCLK/16384.
Bits WDTOE and WDTAE are set to 0 after a power-on hardware reset or software
reset. In case of a reset caused by the WDT, these two bits are set depending on
the error condition that caused the Watchdog reset.
2.2
Time-out Mode is automatically triggered by the following events:
Reset
WDTCON0 is unlocked by a successful password access
Time-out Mode is indicated by WDTSR.WDTTO=1. As the name suggests, Time-out Mode
lasts for a particular duration, called the Time-out Period. Time-out Mode must be exited
before this period is over, or the system is reset.
Time Out Mode and Reset Pre-warning Mode
To disable the Time-out Mode, bit ENDINIT in register WDTCON0 must be written to 1
with a modifying access. This access stops the Time-out, resets bit WDTSR.WDTTO, and
switches the WDT back to the operation determined through WDTSR.WDTDS,
WDTSR.WDTIS and WDTCON0.WDTREL. If WDTDS=1, the Watchdog Timer is reset to 0
and is stopped. If WDTDS=0, the Watchdog Timer is set to the value of
WDTCON0.WDTREL and starts counting upwards with the clock input selected through
WDTIS.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TRR-8A33 | Connectorized High-speed GaAs PIN |
| TRS1722 | KIT INSULATED TERMINAL |
| TRS1755 | 33+3/4X66FT PLSTC TAPE |
| TRS1766 | HIGH SENSITIVITY REFLECTIVE COLOR SENSOR WITH LIGHTTOVOLTAGE CONVERTERS |
| TRU-600 | TRU-600 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TRIDENT SAMPLE CASE | 制造商:ITT Interconnect Solutions 功能描述:TRIDENT SAMPLE CASE / 192993-3000 / Trident |
| TRIG26362-I | 制造商:Pass & Seymour/Legrand 功能描述:IG TR DECOR RECEPT 20A 125V IV |
| TRIG5362-REDSP | 制造商:Pass & Seymour/Legrand 功能描述:IG SPD RECP TR 20A/125V ALARM RED |
| TRIG8300-RED | 制造商:Pass & Seymour/Legrand 功能描述:HG IG TR DUP RECEPT 20A 125V RED |
| TRIG8300-W | 制造商:Pass & Seymour/Legrand 功能描述:HG IG TR DUP RECEPT 20A 125V WH |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。