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參數(shù)資料
| 型號： | TriCore |
| 廠商： | SIEMENS AG |
| 英文描述： | 32-bit microcontrollers(32位微控制器) |
| 中文描述： | 32位微控制器（32位微控制器） |
| 文件頁數(shù)： | 16/17頁 |
| 文件大?。?/td> | 117K |
| 代理商： | TRICORE |
How to use the
Watchdog Timer of the TriCore
16 of 17
AP3219 Rel.02
WDTCON1
Watchdog Control Register 1
Reset Value: 0x0000.0000
Symbol
WDTDR
Position
WDTCON1[3]
Type
Rw
Value
Function
0
1
Watchdog Timer Disable Request Control Bit.
Request to enable the Watchdog Timer.
Request to disable the Watchdog Timer.
This bit can only be modified if ENDINIT is reset to 0. An update of this bit
only goes into effect when ENDINIT is set to 1 again. As long as ENDINIT is
0, bit WDTDS in register WDTSR controls the current enable/disable status
of the Watchdog Timer. When ENDINIT is 1, WDTDS is updated with the
state of bit WDTDR.
WDTIR
WDTCON1[2]
Rw
0
1
Watchdog Timer Input Frequency Request Control Bit.
Request to set input frequency to f SYSCLK /16384.
Request to set input frequency to f SYSCLK /256.
This bit can only be modified if ENDINIT is reset to 0. An update of this bit
only goes into effect when ENDINIT is set to 1 again. As long as ENDINIT is
0, bit WDTIS in register WDTSR controls the current input frequency of
the Watchdog Timer. When ENDINIT is 1, WDTIS is updated with the state
of bit WDTIR.
SCKCLR
WDTCON1[10:8]
Rw
Self check clear request bits.
SCKCLR = <number>: request to clear bit SCKERR[<number>].
When ENDINIT is set to 1, the corresponding bit SCKERR in register
WDTSR will be cleared.
-
R
These bit positions are read-only, returning 0 when read. Writing to these bit
positions has no effect. These positions are reserved for future extensions,
and it is advised to always write a 0 to these bit positions when writing to the
register in order to preserve compatibility with future derivatives.
WDTSR
Watchdog Status Register
Reset Value: 0xFFFC.uu1u
Symbol
WDTTIM
SCKERR
Position
WDTSR[31:16]
WDTSR[15:8]
Type
R
R
Value
Function
Reflects the current contents of the Watchdog Timer.
Self check error bits.
SCKERR[<number>] = 0: Self check <number> passed successfully.
SCKERR[<number>] = 1: Self check <number> not passed
This bits are set to 1 after reset when the self check configuration has been
selected. Each bit of this array can be cleared 1 by
1 through the SCKCLR bits in register WDTCON1. This operation will go into
effect after ENDINIT is written to 1 during a modify access to register
WDTCON0. It is not possible to terminate the self check mode until all
SCKERR bits are cleared.
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