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參數(shù)資料
| 型號： | TriCore |
| 廠商： | SIEMENS AG |
| 英文描述： | 32-bit microcontrollers(32位微控制器) |
| 中文描述： | 32位微控制器（32位微控制器） |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 117K |
| 代理商： | TRICORE |
How to use the
Watchdog Timer of the TriCore
10 of 17
AP3219 Rel.02
Example:
Mask = 0xffff000f;
Modify = 0xabcd000f;
//bits that will be changed set to 1
//new value for WDCON0(here ENDINIT will be set to 1
//and Reset Value to 0xabcd)
WDT_Modify(Modify, Mask);
//Procedure call
4.2
Writing to the register WDTCON1 is only possible if bit ENDINIT is cleared (WDTCON1 is
ENDINIT-protected). You can change only the Watchdog Timer Input Frequency Request
Control Bit (WDTIR) and the Watchdog Timer Disable Request Control Bit (WDTDR).
How to change the WDTCON1
Symbol
WDTDR
Position
WDTCON1[3]
Type
rw
Value
Function
0
1
Watchdog Timer Disable Request Control Bit.
Request to enable the Watchdog Timer.
Request to disable the Watchdog Timer.
As long as ENDINIT is 0, bit WDTDS in register WDTSR controls the current
enable/disable status of the Watchdog Timer. When ENDINIT is 1, WDTDS
is updated with the state of bit WDTDR.
WDTIR
WDTCON1[2]
rw
0
1
Watchdog Timer Input Frequency Request Control Bit.
Request to set input frequency to f
SYSCLK
/16384.
Request to set input frequency to f
/256.
As long as ENDINIT is 0, bit WDTIS in register WDTSR controls the current
input frequency of the Watchdog Timer. When ENDINIT is 1, WDTIS is
updated with the state of bit WDTIR.
Note:
Updates made to the bits in this register will go into effect after WDTCON0.ENDINIT
has been set to 1 again.
4.3
The duration of Normal Timer Mode can be varied by two parameters: the input clock and
the reload value.
The system clock, f
SYSCLK
, can be divided by either 256 or 16384. WDTSR.WDTIS selects
the input clock divider. The default value of WDTIS after reset is 0, corresponding to a
frequency of f
SYSCLK
/16384. When the Watchdog Timer is serviced in Normal Timer Mode,
it is reloaded with the 16-bit reload value, WDTCON0.WDTREL.
The Watchdog Timer period can be varied over a wide range.
The maximum time period is achieved by setting WDTREL=0x0000. The minimum time
period is achieved by setting WDTREL=0xFFFF. The general form with variable reload
value WDTREL for these calculations is:
Normal Timer Period
Period = (2
16
– WDTREL) * 256 * 2
(1 - WDTIS) * 6
/ f
SYSCLOCK
Example:
WDTREL = 0xFFFC = 65532; WDTIS = 1; f
SYSCLOCK
= 100MHz;
Period = (2
16
– WDTREL) * 256 * 2
(1 - WDTIS) * 6
/ f
SYSCLOCK
Period = (2
16
– 65532) * 256 * 2
(1 - 1) * 6
/ 100MHz) = 10,24
μ
s
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