參數(shù)資料
型號： TRF2432_07
廠商： Texas Instruments, Inc.
英文描述： Dual-Band IQ/IF TRANSCEIVER WITH DUAL VCO SYNTHESIZERS
中文描述： 雙頻智商具有雙中頻VCO的合成器/
文件頁數(shù)： 3/24頁
文件大?。?/td> 537K
代理商： TRF2432_07
www.ti.com
DEVICE INFORMATION
TRF2432
SLWS177B–APRIL 2005–REVISED NOVEMBER 2006
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O
TYPE
DESCRIPTION
NAME
RFPD
PAPDA
PAPDB
ABSEL
V+RFLO
GND
LON
LOP
GND
V+CP
RSVD2
RFLOBP
RFLOTUN
RFLOCP
RSVD3
XTALO
V+D
CLKON
XTALBYP
CLKOP
V+CLK
CLK
DATA
EN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
O
O
O
O
I
I
O
O
I
I
-
O
I
O
-
I/O
I
O
O
O
I
I
I
I
Analog
Analog
Analog
Analog
Power
Analog
RF Dif.
RF Dif.
Analog
Power
-
Analog
Analog
Analog
-
Analog
Power
Digital
Analog
Digital
Power
Digital
Digital
Digital
RFFE sleep output
PA band A select to RFFE
PA band B select to RFFE
A or B band select to RFFE
+3.3V Power Supply. RF VCO bias
Connect to ground per suggested layout for normal operation
Positive going LO output
Negative going LO output
Connect to ground per suggested layout for normal operation
+3.3V Power Supply. Synthesizer Charge Pumps bias
Reserved. Leave open
Bypass Capacitor for LO1 (RF)
VCO Synthesizer 1 (RF) Tuning port
Synthesizer 1 (RF) Charge pump output
Reserved. Leave open
Negative crystal connection
+3.3V Power Supply. Digital Bias
Negative going reference clock output (40,44,20 or 22MHz)
Bypass Capacitor for crystal oscillator
Positive going reference clock output (40,44,20 or 22MHz)
+3.3V Power Supply. Reference Clock Bias
Clock line of 3-wire serial bus
Data line of 3-wire serial bus
Load enable line of 3-wire serial bus
A transition high in RX active mode initiates DC offset calibration. Low disables
calibration circuit. Internal pull down
Positive crystal connection. Also input for external XO reference
Connect to ground per suggested layout for normal operation
Sets reference clock divider. Set HIGH to activate divide by 2. Internal pull down.
VCO Synthesizer 2 (IF) Tune port. CP2 Connected internally
Bypass Capacitor for LO2 (IF)
Reserved. Leave open.
PA enable. HIGH enables RFFE PA. Enables PAPDA or PAPDB. Internal pull
down.
Transmit or Receive control line. TX=HIGH, RX=LOW. Internal pull down.
Power enable. HIGH is enabled. Not defined internally.
RF, IF and REF synthesizer lock detect and calibration status.
+3.3V Power Supply. IF VCO bias
Connect to ground per suggested layout for normal operation
Receiver in-phase negative going output.
Receiver in-phase positive going output.
Receiver quadrature negative going output.
Receiver quadrature positive going output.
Connect to ground per suggested layout for normal operation
Transmitter quadrature negative going output.
CALEN
25
I
Digital
XTALI
GND
REFDIV
IFLOTUN
IFLOBP
RSVD1
26
27
28
29
30
31
I/O
I
I
I
O
-
Analog
Analog
Digital
Analog
Analog
-
PAEN
32
I
Digital
TR
PE
STATUS
V+IFLO
GND
RXIN
RXIP
RXQN
RXQP
GND
TXQN
33
34
35
36
37
38
39
40
41
42
43
I
I
Digital
Digital
Digital
Power
Analog
Analog
Analog
Analog
Analog
Analog
Analog
O
I
I
O
O
O
O
I
I
3
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