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參數(shù)資料
| 型號： | TRF2052PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | LOW-VOLTAGE 2-GHz SYNTHESIZER |
| 中文描述： | 低電壓2 - GHz的合成器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 130K |
| 代理商： | TRF2052PW |
TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 – JULY 1998
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 1. Function Table
SYMBOL
BITS
FUNCTION
N
18
Overall main divider integer division ratio
CN
8
Binary current setting factor for main charge pumps
G2
4
MS bits for the speed-up mode duration (number of reference divider cycles)
G1
4
LS bits for the speed-up mode duration (number of reference divider cycles)
CK
4
Binary acceleration factor for integral charge pump current
CL
2
Binary acceleration factor for increase in main charge pump current during speed-up mode
MCP
1
Main charge pump polarity
ACP
1
Auxiliary charge pump polarity
NA
12
Auxiliary divider ratio
PA
1
Auxiliary prescaler select:
0 = divide by 4
1 = divide by 1
NR
12
Reference divider ratio
SM
2
Reference select for main phase detector
EM
1
Main divider enable flag
SA
2
Reference select for auxiliary phase detector
EA
1
Auxiliary divider enable flag
ES
1
Speed-up mode standby control:
0 = speed-up charge pump switches off completely if no fast mode
1 = speed-up charge pump always in standby
PM
1
Phase detector mode. Change between two modes for reset pulse generation:
0 = analog internal generated delay
1 = high-pulse duration for REF-CLOCK
RF inputs
The differential main divider input has a resistance of several k and can be matched to the system impedance
by an external resistor. To form a single ended input, any one of the input pins can be grounded by a blocking
capacitor.
The auxiliary channel RF and reference inputs have a high resistance, as well, and are single ended. If needed,
matching can be accomplished with an external resistor.
enabling the PLLs
Both PLLs can be enabled and disabled independently, either by the serial control variables EM and EA or by
the digital inputs pins NENM and NENA.
The serial control variables and the hardware signal NENM disable the charge pump and the divider of the
corresponding loop, while NENA affects the auxiliary charge pump output only. This helps to avoid spikes that
might occur after re–enabling the auxiliary loop by the serial interface.
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