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參數(shù)資料
| 型號： | TRF2052PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | LOW-VOLTAGE 2-GHz SYNTHESIZER |
| 中文描述： | 低電壓2 - GHz的合成器 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 130K |
| 代理商： | TRF2052PW |
TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 – JULY 1998
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
charge pump output currents
The steepness of the phase detector charge-pump chains is determined by external resistors between the
dedicated pins RA and RN and ground, as well as by user programmable variables. The charts that follow
indicate how the charge-pump peak currents can be set by the external resistors and the control variables.
auxiliary charge pump
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
|IPHA|
Open loop mode (NENA = 1)
0
VPHA
VDDA
10
pA
|IPHA|
Closed loop mode (NENA = 0)
0.5 V
RA
VPHA
= 18 k
VDDA – 0.5 V,
20
×
1.25/RA[k
]
mA
main charge pump
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
|IPHM_N|
Normal mode
0.5 V
RN
VPHP
= 18 k
VDDA – 0.5 V,
18.75/(RN[k
] + 0.75)
×
CN/256
mA
|IPHM_S|
Speed-up mode (see Note 4)
|IPHM_N|
×
(1 + 2CL + 1)
mA
4. The maximum allowable current is 12 mA. It is recommended to use the speedup mode only before the PLL is locked. Switching
between speedup and normal modes as well as changing the current setting factor CN, under PLL operation, may cause
disturbances in the VCO control voltage.
integral charge pump
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
|IPHI_N|
Normal mode
0
VPHI
VDDA
0
mA
|IPHI_S|
Speed-up mode (see Note 5)
0.5 V
RN
|IPHM_S|
VPHI
= 18 k
,
VDDA – 0.5 V,
16 mA
|IPHM_N|
×
2CL + 1
×
CK
mA
5. Maximum allowable current is 24 mA
The instantaneous values of the charge pump currents are related to the phase error by:
IPH_inst
error
2
IPH_peak
modes of operation
CHIP MODE
NENM
NENA
ACTIVE STAGES
Both synthesizers on
0
0
Everything on
Main synthesizers on
0
1
Only auxiliary charge pump set to triple state; everything else working
Auxiliary synthesizer on
1
0
Main loop disabled, auxiliary loop working
Shutdown
Enable signals, NENM and NENA, are active low.
1
1
All off
timing requirements, serial data interface (see Figure 1)
PARAMETER
MIN
MAX
UNIT
f(CLOCK)
tw(CLKHI)
tw(CLKLO)
tsu(D)
th(D)
tsu(STROBE)
tw(STROBEHI)
tw(STROBELO)
Clock frequency
10
MHz
Clock high-time pulse width, Clock high
30
ns
Clock low-time pulse width, Clock low
Set-up time, data valid before CLOCK
↑
Hold time, data valid after CLOCK
↑
Set-up time, STROBE
↑
before CLOCK
↑
STROBE high-time pulse width, STROBE high
30
ns
30
ns
30
ns
30
ns
30
ns
STROBE low-time pulse width, STROBE low
30
ns
(1)
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