
TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 – JULY 1998
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
Serial Control Shift Register
Control and Selection
Internal Control Register
Band Gap
and Bias
DATA
CLOCK
STROBE
NENM
NENA
Main Divider
N
Main Phase
Detector
MCP
1/–1
Speed-Up
Counter
G
Main
Charge Pump
CN
CL
Intergral
Charge Pump
CK
SELECT
SELECT
1 2 4 8
Reference
Divider
M
SM
2
Lock
Detector
Auxiliary
Divider
NA
Auxiliary
Phase Detector
ACP
1/–1
4/1
PA
Auxiliary
Charge Pump
PHP
RN
PHI
LOCK
RA
PHA
RFINP
RFINN
REFIN
AUXIN
2
1
3
19
17
5
6
8
10
14
16
13
18
9
11
18
12
12
8
8
2
4
SA
2
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
10
AUXIN
Auxiliary channel RF input
CLOCK
1
Serial interface clock signal
DATA
2
Serial interface data signal
LOCK
18
Lock detector output
NENA
17
Enable signal for the auxiliary channel/main channel/open loop. See modes of operation logic table. Active low
NENM
19
Enable signal for the auxiliary channel/main channel/open loop. See modes of operation logic table. Active low
PHA
11
Auxiliary charge pump output
PHI
13
Integral charge pump output
PHP
14
Main (proportional) charge pump output
RA
9
Resistor to VSSA sets auxiliary charge pump current
REFIN
8
Reference frequency input signal
RFINN
6
Prescaler negative RF input
RFINP
5
Prescaler positive RF input
RN
16
Resistor to VSSA sets main charge pump current
STROBE
3
Serial interface load signal
VCCP
7
Prescaler positive supply voltage
VDD
20
Digital supply voltage
VDDA
15
Analog supply voltage
VSS
4
Digital/prescaler ground
VSSA
12
Analog ground