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參數(shù)資料
| 型號： | TRC102 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | 400-1000MHz RF Transceiver |
| 中文描述： | 400 - 1000MHz的射頻收發(fā)器 |
| 文件頁數(shù)： | 32/40頁 |
| 文件大小： | 449K |
| 代理商： | TRC102 |
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32
PLL Configuration Register
[POR=CC67h]
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
1
1
0
0
The PLL Configuration Register configures the following:
Output Clock buffer slew rate
Crystal start-up time
Phase Detector Delay (PDD)
PLL Dithering
PLL Bandwidth
Bit [15..8] - Command Code
: These bits are the command code that is sent serially to the processor
that identifies the bits to be written to the PLL Configuration Register.
Bit [7] – Not Used
: Write a ‘0’.
Bit [6..5] – Clock Buffer Slew
: These bits set the rise and fall times for the clock buffer dependant on
the output frequency. See table 17 below.
Table 17.
Freq
>5 MHz
3 MHz
<2.5 MHz
Bit [4] – Crystal Start-up Time
: This bit sets the start-up time and current consumption of the crystal.
See table 18 below.
Table 18.
Time
Current
1ms
620uA
2 ms
460uA
Bit [3] - Phase Detector Delay
: When set, this bit enables the delay function.
Bit [2] – PLL Dithering
: When set, this bit disables dithering. Dithering reduces the noise error when
calculating the fractional-N synthesizer code. When clear, dithering is enabled and settle time is
increased slightly.
Bit [1] – Not Used
: Write a ‘1’.
Bit [0] – PLL Bandwidth
: When set, this bit increases the PLL bandwidth slightly to accommodate
higher data rates above 90kbps. When clear, the PLL bandwidth is reduced which allows for faster
settling and reduced phase noise resulting in better RX performance. See Table 19 below.
Table 19.
Data Rate
Phase Noise
<90 kbps
-107 dBc/Hz
>90 kbps
-102 dBc/Hz
Bit
10
1
Bit
9
0
Bit
8
0
Bit
7
0
Bit
6
BUF1
Bit
5
BUF0
Bit
4
XSU
Bit
3
PDD DITH
Bit
2
Bit
1
1
Bit
0
1
PLLBW
BUF1
0
0
1
BUF0
0
1
X
XSU
0
1
PLLBW
0
1
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