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參數(shù)資料
| 型號： | TRC102 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | 400-1000MHz RF Transceiver |
| 中文描述： | 400 - 1000MHz的射頻收發(fā)器 |
| 文件頁數(shù)： | 31/40頁 |
| 文件大?。?/td> | 449K |
| 代理商： | TRC102 |
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31
Battery Detect Threshold and Clock Output Register
[POR=C000h]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
1
1
0
0
0
0
0
The Battery Detect Threshold and Clock Output Register configures the following:
Low Battery Detect Threshold
Output Clock frequency
The Low Battery Threshold is programmable from 2.2V to 3.8V using the following equation:
VT = (LBD[4..0] / 10) + 2.2 (V)
where LBD[3..0] is the decimal value 0 to 15.
Bit [15..8] - Command Code
: These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the
Battery Detect Threshold and Clock Output Register
.
Bit [7..5] – Clock Output Frequency
: These bit set the output frequency of the on-board clock that may
be used to run an external host processor. See Table 16 below.
TABLE 16.
Bit [4..0] – Low Battery Detect Value
: These bits set the decimal value as used in the equation above to
calculate the value of the battery detect threshold voltage. When the battery level falls 50mV below this
value, the LBD bit (5) in the status register is set indicating that the battery level is below the programmed
threshold. This is useful in monitoring discharge sensitive batteries such as Lithium cells.
The Low Battery Detect can be enabled by setting the LBDEN bit (2) of the
Power Management Register
and disabled by clearing the bit.
The Clock Output can be enabled by setting the CLKEN bit (0) of the
Power Management Register
and
disabled by clearing the bit.
Bit
8
0
Bit
7
CLK2
Bit
6
CLK1
Bit
5
CLK0
Bit
4
0
Bit
3
LBD3 LBD2 LBD1
Bit
2
Bit
1
Bit
0
LBD0
Output Clock Frequency (MHz)
1
1.25
1.66
2
2.5
3.33
5
10
CLK2
0
0
0
0
1
1
1
1
CLK1
0
0
1
1
0
0
1
1
CLK0
0
1
0
1
0
1
0
1
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