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參數(shù)資料
| 型號： | TRC102 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | 400-1000MHz RF Transceiver |
| 中文描述： | 400 - 1000MHz的射頻收發(fā)器 |
| 文件頁數(shù)： | 3/40頁 |
| 文件大?。?/td> | 449K |
| 代理商： | TRC102 |
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3
1
2
SDI
SCK
nCS
SDO
IRQ
3
4
5
6
7
8
DATA/nFSEL
CR/FINT/FCAP
CLKOUT
nINT/DDET
RSSIA
VDD
RF_N
RF_P
GND
RESET
Xtal/Ref
TOP VIEW
TRC102
9
10
11
12
13
14
15
16
1. Pin Configuration
1.1 Pin Descriptions
Pin Name
1
SDI
2
SCK
3
nCS
Description
SPI Data In
SPI Data Clock
Chip Select Input
– Selects the chip for an SPI data transaction. The pin must be pulled ‘low’ for a 16-
bit read or write function. See Figure 6 for timing specifications.
SPI Data Out
4
5
SDO
nIRQ
Interrupt Request Output
- The receiver will generate an active low interrupt request for the
microcontroller on the following events:
· The TX register is ready to receive the next byte
· The FIFO has received the preprogrammed amount of bits
· Power-on reset
· FIFO overflow/TX register underrun
· Wake-up timer timeout
· Negative pulse on the interrupt input pin nINT
· Supply voltage below the preprogrammed value is detected
Data In
– When the internal TX register is not used, this pin may be used to manually modulate data
from an external host processor. If the internal TX register is enabled, this pin may be left unconnected
or tied “High”. When using the internal Rx FIFO, this pin must be pulled “Low”. This pin is used to
select the internal registers when reading and writing.
Data Out
– When the internal FIFO is not used this pin is used in conjunction with pin 7 (Recovered
Clock) to receive data.
FIFO Select
– When reading the RX FIFO, this pin selects the FIFO and the first bit appears on the next
clock. Use this pin in conjunction with Pin 7. This pin is internally pulled “High” when accessing the TX
register. Leave this pin “High” when the TX register is enabled. For minimum current consumption do
NOT pull this pin “Low” in Sleep Mode.
Recovered Clock Output
– When the digital filter is used (
Baseband Filter Register
, Bit [4]) and FIFO
disabled (
Configuration Register,
Bit [6]), this pin provides the recovered clock from the incoming data.
FIFO INT
– When the internal FIFO is enabled (
Configuration Register,
Bit [6]), this pin acts as a FIFO
Full interrupt indicating that the FIFO has filled to its pre-programmed limit (
FIFO Configuration Register
,
Bit [7..4]).
External Data Filter Capacitor
– When the Analog filter is used (
Baseband Filter Register
, Bit [4]), this
pin is the raw baseband data that may be used by a host processor for data recovery. The external
capacitor forms a simple lowpass filter with an internal 10KOhm series resistor. The capacitor value
may be chosen for a Max data rate up to 256kbps.
Optional host processor Clock Output
Xtal
- Connects to a 10MHz series crystal or an external oscillator reference.
The circuit contains an
integrated load capacitor (See
Configuration Register
) in order to minimize the external component
count. The crystal is used as the reference for the PLL, which generates the local oscillator frequency.
The accuracy requirements for production tolerance, temperature drift and aging can be determined
from the maximum allowable local oscillator frequency error. Whenever a low frequency error is
essential for the application, it is possible to “pull” the crystal to the accurate frequency by changing the
load capacitor value.
Ext Ref
– An external reference, such as an oscillator, may be connected as a reference source.
Connect through a .01uF capacitor.
Reset Output
with internal pull-up
System Ground
RF Diff I/O
RF Diff I/O
Supply Voltage
6
Data/nFSel
7
CR/FINT/FCAP
8
9
ClkOut
Xtal/Ref
10
11
12
13
14
15
nRESET
GND
RF_P
RF_N
VDD
RSSIA
Analog RSSI Output –
The Analog RSSI can be used to determine the actual signal strength. The
response and settling time depends on an external filter capacitor. Typically, a 1000pF capacitor will
provide optimum response time for most applications.
16
nINT/DDet
nINT
– This pin may be configured as an active low external interrupt to the chip. When a logic ‘0’ is
applied to this pin, it causes the nIRQ pin (5) to toggle, signaling an interrupt to an external processor.
Reading the first four (4) bits of the status register tells the source of the interrupt. This pin may be used
as a wake-up event from sleep.
Valid Data Detector Output
– This pin may be configured to indicate Valid Data when the synchronous
pattern recognition circuit indicates potentially real incoming data.
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