參數(shù)資料
型號(hào)： TRC102
廠商： RF Monolithics, Inc.
英文描述： 400-1000MHz RF Transceiver
中文描述： 400 - 1000MHz的射頻收發(fā)器
文件頁(yè)數(shù)： 24/40頁(yè)
文件大?。?/td> 449K
代理商： TRC102
24
FIFO and RESET Mode Configuration Register
[POR=CA80h]
Bit Bit Bit Bit Bit Bit Bit Bit
15 14 13 12 11 10
9
1
1
0
0
1
0
1
The Data FIFO Configuration Register configures:
FIFO fill interrupt condition
FIFO fill start condition
FIFO fill on synchronous pattern
Synchronous Character Length
RESET Mode
Bit [15..8] - Command Code
: These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the Data FIFO Configuration Register.
Bit [7..4] – FIFO Fill Bit Count
: This sets the number of bits that are received before generating an
external interrupt to the host processor that the receive FIFO data is ready to be read out. It is possible to
set the maximum fill level to 15, but the designer must account for the processing time it will take to read
out the data before a register overrun occurs, at which data will be lost. It is recommended to set the fill
value to half of the desired number of bits to be read to ensure enough time for additional processing.
See Status Register for description of FIFO status bits that may be read and FIFO Read Register for
polling and interrupt-driven FIFO reads from the SPI bus.
Bit [3] – Synchronous Character Length:
This bit sets the length of the synch character to either byte
or word long. When set to word long the character is composed of 2 bytes SB1 and SB0. The value of
SB1 is fixed and is not configurable. The value of SB0 is user programmable through the
Synch Byte
Configuration Register
. When set to byte long only SB0 is used and is user programmable.
Note:
Default POR value of SB0 is D4h.
Table 15.
Synch Character
SBL
2DXX (Word Long)
0
XX (Byte Long)
1
Bit [2] – FIFO Fill Start Condition
: This bit sets the condition at which the FIFO begins filling with data.
When set, the FIFO will continuously fill regardless of noise or good data. When clear, the FIFO will fill
when it recognizes the synchronous pattern as defined internally.
Bit [1] – Synchronous Pattern FIFO Fill
: When set, the FIFO will begin filling with data when it detects
the synchronous pattern as defined in Bit [2]. The FIFO fill stops when this bit is cleared. To restart the
synchronous pattern recognition, simply clear the bit and set again.
Note:
Clearing this bit will issue a FIFO reset. See Figure 9 for FIFO write and reset
configuration.
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
8
0
FINT3
FINT2
FINT1
FINT0
SBL
FIFST
FILLEN
RSTEN
SB1
2D
N/A
SB0
D4
(programmable)
D4
(programmable)
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