參數(shù)資料
型號: TRC102
廠商: RF Monolithics, Inc.
英文描述: 400-1000MHz RF Transceiver
中文描述: 400 - 1000MHz的射頻收發(fā)器
文件頁數(shù): 23/40頁
文件大小: 449K
代理商: TRC102
23
FIFO Read Register
[POR=B000h]
Bit
Bit
Bit
Bit
15
14
13
12
1
0
1
1
The FIFO Read Register stores the received data and can be read out by the host processor. The FIFO
must be enabled by setting Bit[6] of the
Configuration Register
.
Bit [15..8] - Command Code
: These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the
Data FIFO Configuration Register
.
Bit [7..0] – FIFO Data Bits
: These bits are the recovered data bits stored in the FIFO. These bits may be
read out over the SPI bus.
*Alternate Read Method
The Rx FIFO is directly accessible by using the nFSEL select pin (6) and monitoring the FINT interrupt pin
(7) for pending data. Each data bit may be clocked in on the rising edge of SCK.
Bit
11
0
Bit
10
0
Bit
9
0
Bit
8
0
Bit
7
RX7
Bit
6
RX6
Bit
5
RX5
Bit
4
RX4
Bit
3
RX3
Bit
2
RX2
Bit
1
RX1
Bit
0
RX0
Figure. 8 Recommended FIFO Read Method Timing
*NOTE: The internal FIFO cannot be accessed faster than f
XTAL
/4 when reading the
FIFO or data errors will occur. For a 10MHz ref xtal the max SCK <2.5MHz.
SCK
nCS
SDO
nFSEL
nFINT
D7
D6
D5
D4
D3
D2
D1
D0
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