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參數(shù)資料
| 型號： | TRC102 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | 400-1000MHz RF Transceiver |
| 中文描述： | 400 - 1000MHz的射頻收發(fā)器 |
| 文件頁數(shù)： | 14/40頁 |
| 文件大?。?/td> | 449K |
| 代理商： | TRC102 |
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14
Configuration Register
[POR=8008h]
Bit
Bit
Bit
Bit
15
14
13
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
1
0
0
0
0
0
0
0
DATEN
FIFEN
BAND1
BAND0
CAP3
CAP2
CAP1
CAP0
The configuration register sets up the following:
Internal Data Register
Internal FIFO
Frequency Band in use
Crystal Load capacitance
Bit [15..8] – Command Code
: These bits are the command code that is sent serially to the processor
that identifies the bits to be written to the configuration register.
Bit [7] – Data Register Enable
: This bit enables the internal data register when set. If the internal data
register is used, the FSK pin (6) must be connected to GND.
Bit [6] – FIFO Enable
: This bit enables the internal data FIFO when set. The FIFO is used to store data
during receive. If the FIFO is disabled by clearing this bit, pin 6 (Data) and pin 7 (Recovered Clock) are
used to receive data. See Data Buffer Setup Register section for details on the FIFO configuration.
Bit [5..4] – Band Select
: These bits set the frequency band to be used. There are four (4) bands that are
supported. See Table 3 below for Band configuration.
TABLE 3.
Bit [3..0] – Load Capacitance Select
: These bits set the load capacitance for the crystal reference. The
internal load capacitance can be varied from 8.5pF to 16pF in 0.5pF steps to accommodate a wide range
of crystal vendors as well as adjust the reference frequency and compensate for stray capacitance that
may be introduced due to PCB layout. See Table 4 below for load capacitance configuration.
TABLE 4.
Frequency Band
433
868
916
BAND1
0
1
1
BAND0
1
0
1
CAP3 CAP2
CAP1
CAP0
Crystal Load
Capacitance
8.5
9
9.5
10
……
15.5
16
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
……
1
1
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