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參數(shù)資料
| 型號： | TRC102 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | 400-1000MHz RF Transceiver |
| 中文描述： | 400 - 1000MHz的射頻收發(fā)器 |
| 文件頁數(shù)： | 13/40頁 |
| 文件大?。?/td> | 449K |
| 代理商： | TRC102 |
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13
Status Register
(Read Only)
Bit
Bit
14
13
Bit
15
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
FIFTXRX
POR
FIFOV/UR
WKINT
INTRST
LB
FIFEMP
RSSI/AT
GDQD
CRLCK
AFATGL
OFFSGN
OFF3
OFF2
OFF1
OFF0
The Status Register provides feedback for:
FIFO ready/full/empty/under run/overwrite
POR
Interrupt state
Low Battery
Good Data Quality
Digital RSSI signal level
Clock Recovery
Frequency Offset value and sign
AFA
Note
: The Status Register read command begins with a logic ‘0’ where all other register commands begin with a logic ‘1’.
Bit [15]:FIFTXRX
– When set, indicates the transmit register is ready to receive the next byte for transmission (Transmit Mode) or
that the Rx FIFO has reached the preprogrammed limit (Receive Mode). This bit is multiplexed and dependent
on whether you are in the respective Transmit or Receive mode. (Cleared when FIFO read).
Bit [14]:POR
– When set, Power-on Reset occurred. (Cleared after Status Reg read).
Bit [13]:FIFOV/UR
– When set, indicates transmit register under run or register overwrite (Transmit Mode) or receive FIFO overflow
(Receive Mode). (Cleared after Status Reg read).
Bit [12]:WKINT
– When set, indicates a Wake-up timer overflow. (Cleared after Status Reg read).
Bit [11]:INTRST
– When set, indicates a High to Low logic level change on interrupt pin (pin 16). (Cleared after Status Reg read).
Bit [10]:LB
– When set, indicates the supply voltage is below the preprogrammed limit. See Battery Detect Threshold and Clock
Output Register.
Bit [9]:FIFEMP
– When set, indicates receive FIFO is empty.
Bit [8]:RSSI(Rx)
– When set and chip in receive mode, this bit indicates that the incoming RF signal is above the preprogrammed
Digital RSSI limit.
AT(TX
) – When in transmit mode this bit indicates that the antenna tuning circuit has detected a strong enough RF signal.
Bit [7]:GDQD
– When set, indicates good data quality.
Bit [6]:CRLCK
– When set, indicates Clock Recovery is locked.
Bit [5]:AFATGL
– For each AFC cycle run, this bit will toggle between logic ‘1’ and logic ‘0’.
Bit [4]:OFFSGN
– Indicates the difference in frequency is higher (logic ‘1’) or lower (logic ‘0’) than the chip frequency.
Bit [3..0]:OFF[3..0]
– The offset value to be added to the frequency control word (internal PLL).
To read the status register, initiate a command beginning with a ‘0’ and read the remaining bits on the SDO line. All other
commands begin with a ‘1’ so the TRC102 recognizes a command vs. status. See figure 4 for timing reference.
Figure 4. Status Read Timing
nCS
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