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參數(shù)資料
| 型號： | TR8100 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | 916.50 MHz Hybrid Transceiver |
| 中文描述： | 916.50兆赫混合收發(fā)器 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 431K |
| 代理商： | TR8100 |
RF Monolithics, Inc.
RFM Europe
1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
Phone: (972) 233-2903
Phone: 44 1963 251383
Fax: (972) 387-8148
Fax: 44 1963 251510
E-mail: info@rfm.com Page 12 of 14
http://www.rfm.com
TR8100-021307
Control Register Read/Write Timing
Pin 19
Pin 18
Pin 17
Write Cycle Timing
Pin 18
Pin 19
Pin 17
Read Cycle Timing
X
R/W
A1
D0
X
A0
D7
D0
T
C1RDZ
T
C1RDVAL
T
CFGHLD
T
C1RLS
T
CFGLO
T
CFGHLD
T
C0HI
T
C0LO
T
C0PD
T
C1HLD
T
C1SU
T
CFGSU
T
C0SU
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
T
C0SU
CFGCLK (18) low setup time to CFG (19) rising edge
45
ns
T
C0HI
CFGCLK (18) high time
90
ns
T
C0LO
CFGCLK (18) low time
90
ns
T
C0PD
CFGCLK (18) period - rising edge to rising edge
190
ns
T
CFGSU
CFG (19) setup time - active modes
90
ns
all modes except sleep
T
CFGSU
CFG (19) setup time - sleep mode
1000
ns
sleep mode
T
C1SU
CFGDAT (17) setup time to CFGCLK (18) rising edge
45
ns
T
C1HLD
CFGDAT (17) hold time to CFGCLK (18) rising edge
90
ns
T
CFGLO
CFG (19) low time between transfers
90
ns
T
C1RDZ
CFGDAT (17) high impedance setup time on data read
20
ns
T
C1RDVAL
CFGDAT (17) time to valid data output on read
90
ns
T
C1RLS
CFGDAT (17) time to high impedance on end of transfer
20
ns
Read/Write Timing Table
Command
R/W
Address
CFG0
CFG1
Receive OOK using external data and clock recovery
0
00
0000 0000
0000 0000
Receive OOK using internal 19.2 kb/s data and clock recovery
0
00
0000 0001
0000 0100
Transmit OOK with “digital modulation” (FCC 15.247)
0
00
0100 1000
0010 0000
Sleep
0
00
1000 0000
0000 0000
TR8100 Binary Mode Control Strings (send left to right)
Figure 5
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