參數(shù)資料
型號： TR8001
廠商： RF Monolithics, Inc.
英文描述： 868.35 MHz Hybrid Transceiver
中文描述： 868.35兆赫混合收發(fā)器
文件頁數(shù)： 3/14頁
文件大小： 159K
代理商： TR8001
RF Monolithics, Inc.
RFM Europe
1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
Phone: (972) 233-2903
Phone: 44 1963 251383
Fax: (972) 387-8148
Fax: 44 1963 251510
E-mail: info@rfm.com Page 3 of 14
http://www.rfm.com
TR8000-08172007
TX Data
RX Clock
RX Data
TOP VIEW
CFG
CFG
CLK
CFG
DAT
GND
3
RXD
CLK
THLD
1
THLD
2
RREF
GND2
LPF
ADJ
TX
MOD
RX
DATA
CMP
IN
BB
OUT
PK
DET
VCC
3
VCC
1
VCC
2
RFIO
GND1
+ 3
VDC
3G ASH Transceiver Application Circuit
3G OOK/ASK Configuration
1
20
2
3
4
5
6
7
8
9
R
LPF
10
11
12
13
14
15
16
17
18
19
+ 3
VDC
R
TH1
R
TH2
R
REF
R
TXM
C
BBO
C
PKD
C
DCB
L
AT
L
ESD
C
RFB
Host
Microcontroller
L
RFB
CAUTION: Electrostatic Device. Observe precautions when handling.
Item
Symbol
OOK
OOK
ASK
Units
Notes
Encoded Data Rate
DR
NOM
4.8
19.2
115.2
kb/s
see pages 1 & 2
Minimum Signal Pulse
SP
MIN
208.32
52.08
8.68
μs
single bit
Maximum Signal Pulse
SP
MAX
833.28
208.32
34.72
μs
4 bits of same value
PKDET Capacitor
C
PKD
0.022
0.0056
820 pF
μF
±10% ceramic
BBOUT Capacitor
C
BBO
0.01
0.0027
390 pF
μF
±10% ceramic
TXMOD Resistor
R
TXM
6.2
6.2
6.2
K
±5%, for 10 dBm output
LPFADJ Resistor
R
LPF
470
160
24
K
±5%
RREF Resistor
R
REF
100
100
100
K
±1%
THLD2 Resistor
R
TH2
-
-
100
K
±1%, typical values
THLD1 Resistor
1
R
TH1
20
20
20
K
±1%, typical values
DC Bypass Capacitor
C
DCB
4.7
4.7
4.7
μF
tantalum
RF Bypass Capacitor
C
RFB
100
100
100
pF
±5% NPO
Series Tuning Inductor
L
AT
10
10
10
nH
50 ohm antenna
Shunt Tuning/ESD Inductor
L
ESD
100
100
100
nH
50 ohm antenna
RF Bypass Bead
L
RFB
Fair-Rite
Fair-Rite
Fair-Rite
2506033017YO or equivalent
Tranceiver Set-Up, 3.0 Vdc, -40 to +85 °C
TX Data
RX Data
TOP VIEW
CFG
CFG
CLK
CFG
DAT
GND
3
RXD
CLK
THLD
1
THLD
2
RREF
GND2
LPF
ADJ
TX
MOD
RX
DATA
CMP
IN
BB
OUT
PK
DET
VCC
3
VCC
1
VCC
2
RFIO
GND1
+ 3
VDC
3G ASH Transceiver Application Circuit
2G Default OOK/ASK Configuration
1
20
2
3
4
5
6
7
8
9
R
LPF
10
11
12
13
14
15
16
17
18
19
+ 3
VDC
R
TH1
R
TH2
R
REF
R
TXM
C
BBO
C
PKD
C
DCB
L
AT
L
ESD
C
RFB
Host
Microcontroller
L
RFB
Notes:
1.
When using internal data and clock recovery, a THLD1 value of 47K is recommended to minimize start vector “nuisance tripping” due
to random noise.
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