
Pin
Name
Description
15
PWIDTH
The PWIDTH pin sets the width of the ON pulse to the first RF am pli ier t
with a re sis or R
to ground (the ON
pulse width to the sec ond RF am pli ier t
PW2
is set at 1.1 times the pulse width to the first RF am pli ier). The ON
pulse width t
PW1
can be ad usted be ween 0.55 and 1 μs with a re sis or value in the range of 200 K to 390 K. The
value of R
PW
is given by:
R
PW
= 404* t
PW1
- 18.6, where t
PW1
is in μs and R
PW
is in kilohms
A ±5% re sis or value is rec om mended. When this pin is con nected to Vcc through a 1 M re sis or, the RF am pli i
ers op er ate at a nom nal 50%-50% duty cy cle, fa cil at ng high data rate op er a ion. In this case, the RF am pli ier
ON times are con rolled by the PRATE re sis or as de scribed above. It is im por ant to keep the to al ca pac ance
be ween ground, Vcc and this node to less than 5 pF to main ain sta bil ty. When us ng the high data rate op er a ion
with the sleep mode, con nect the 1 M re sis or be ween this pin and CNTRL1 (Pin 17), so this pin is low in the
sleep mode.
16
VCC2
VCC2 is the pos ive sup ply volt age pin for the re ceiver RF sec ion and trans mit er os cil a or. Pin 16 must be by
passed with an RF ca pac or, and must also be by passed with a 1 to 10 μF tan a um or elec ro ytic ca pac or. See
the
ASH Trans ceiver De signer’s Guide
for ad di ional in or ma ion.
17
CNTRL1
CNTRL1 and CNTRL0 se ect the re ceive and trans mit modes. CNTRL1 and CNTRL0 both high place the unit in
the re ceive mode. CNTRL1 high and CNTRL0 low place the unit in the ASK trans mit mode. CNTRL1 low and
CNTRL0 high place the unit in the OOK trans mit mode. CNTRL1 and CNTRL0 both low place the unit in the
power-down (sleep) mode. CNTRL1 is a high-impedance in put (CMOS com pat ble). An in put volt age of 0 to
300 mV is in er preted as a logic low. An in put volt age of Vcc - 300 mV or greater is in er preted as a logic high. An
in put volt age greater than Vcc + 200 mV should not be ap plied to this pin. A logic high re quires a max mum
source cur ent of 40 μA. A logic low re quires a max mum sink cur ent of 25 μA (1 μA in sleep mode). This pin
must be held at a logic level; it can not be left un con nected.
18
CNTRL0
CNTRL0 is used with CNTRL1 to con rol the re ceive and trans mit modes of the trans ceiver. CNTRL0 is a
high-impedance in put (CMOS com pat ble). An in put volt age of 0 to 300 mV is in er preted as a logic low. An in put
volt age of Vcc - 300 mV or greater is in er preted as a logic high. An in put volt age greater than Vcc + 200 mV
should not be ap plied to this pin. A logic high re quires a max mum source cur ent of 40 μA. A logic low re quires a
max mum sink cur ent of 25 μA (1 μA in sleep mode). This pin must be held at a logic level; it can not be left un
con nected.
19
GND3
GND3 is an IC ground pin. It should be con nected to GND1 by a short, low in duc ance trace.
20
RFIO
RFIO is the RF in put/out put pin. This pin is con nected di ectly to the SAW fil er trans ducer. An ennas pre sent ng
an im ped ance in the range of 35 to 72 ohms re sis ive can be sat s ac o ily matched to this pin with a se ies match
ing coil and a shunt match ng/ESD pro ec ion coil. Other an enna im ped ances can be matched us ng two or three
com po nents. For some im ped ances, two inductors and a ca pac or will be re quired. A DC path from RFIO to
ground is required for ESD pro ec ion.
11
SM-20H PCB Pad Layout
Dimensions in inches.
.09
.370
0.000
.065
.105
.145
.185
.225
.265
.305
.345
.435