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參數(shù)資料
| 型號： | TQFN34-20 |
| 廠商： | ANADIGICS, Inc. |
| 英文描述： | Four-Channel Backlight Driver with Dual LDOs |
| 中文描述： | 四通道雙LDO的背光驅(qū)動器 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 392K |
| 代理商： | TQFN34-20 |
AAT2847
Four-Channel Backlight Driver with Dual LDOs
16
2847.2007.09.1.0
LDOs require a 2.2μF or greater output capacitor.
The required input capacitor (C
IN
) is 2.2μF or
greater.
Ceramic capacitors offer many advantages over
their tantalum and aluminum electrolytic counter-
parts. A ceramic capacitor typically has very low
ESR, is lowest cost, has a smaller printed circuit
board (PCB) footprint, and is non-polarized. Low
ESR ceramic capacitors maximize charge pump
transient response.
Before choosing a particular capacitor, verify the
capacitor’s performance with the characteristics
illustrated in the component’s data sheet.
Performance verification will help avoid undesirable
component related performance deficiencies.
PCB Layout
To achieve adequate electrical and thermal per-
formance, careful attention must be given to the
PCB layout. In the worst-case operating condition,
the chip must dissipate considerable power at full
load. Adequate heat-sinking must be achieved to
ensure intended operation.
Figures 5 and 6 illustrate an example PCB layout.
The bottom of the package features an exposed
metal pad. The exposed pad acts, thermally, to
transfer heat from the chip and, electrically, as a
ground connection.
The junction-to-ambient thermal resistance (θ
JA
) for
the connection can be significantly reduced by fol-
lowing a couple of important PCB design guidelines.
The PCB area directly underneath the package
should be plated so that the exposed paddle can be
mated to the top layer PCB copper during the reflow
process. Multiple copper plated thru-holes should
be used to electrically and thermally connect the top
surface pad area to additional ground plane(s).
The chip ground is internally connected to both the
exposed pad and to the AGND and PGND pins. It is
good practice to connect the GND pins to the
exposed pad area with traces as shown in Figure 4.
The flying capacitors (C1 and C2), input capacitor
(C4), and output capacitors (C3, C5, and C6) should
be connected as close as possible to the IC. In addi-
tion to the external passive components being placed
as close as possible to the IC, all traces connecting
the AAT2847 should be as short and wide as possible
to minimize path resistance and potential coupling.
Figure 4: AAT2847 Package Layout.
Pin#1
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