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APPLICATION INFORMATION
Board Layout Recommendation to Improve
PSRR and Noise Performance
To improve ac measurements like PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for V
IN
and V
OUT
, with each ground plane connected
only at the ground pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the ground pin of the device.
GND
EN
NR
IN
OUT
V
IN
V
OUT
0.01
μ
F
TPS796xx
2.2
μ
F
1
μ
F
External Capacitor Requirements
Although not required, it is good analog design
practice to place a 0.1-μF — 2.2-μF capacitor near
the input of the regulator to counteract reactive input
sources. A 2.2-μF or larger ceramic input bypass
capacitor, connected between IN and GND and
located close to the TPS796xx, is required for stability
and improves transient response, noise rejection, and
ripple rejection. A higher-value input capacitor may be
necessary if large, fast-rise-time load transients are
anticipated and the device is located several inches
from the power source.
Regulator Mounting
The tab of the SOT223-6 package is electrically
connected to ground. For best thermal performance,
the tab of the surface-mount version should be
soldered directly to a circuit-board copper area.
Increasing the copper area improves heat dissipation.
Programming the TPS79601 Adjustable LDO
Regulator
The output voltage of the TPS79601 adjustable
regulator is programmed using an external resistor
divider as shown in Figure 28. The output voltage is
calculated using Equation 1:
VO
VREF
1
R1
R2
(1)
TPS79601, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633
SLVS351D–SEPTEMBER 2002–REVISED OCTOBER 2004
The TPS796xx family of low-dropout (LDO) regulators
has been optimized for use in noise-sensitive equip-
ment. The device features extremely low dropout
voltages, high PSRR, ultralow output noise, low
quiescent current (265 μA typically), and enable input
to reduce supply currents to less than 1 μA when the
regulator is turned off.
For example, the TPS79630 exhibits 40 μV
RMS
of
output voltage noise using a 0.1-μF ceramic bypass
capacitor and a 10-μF ceramic output capacitor. Note
that the output starts up slower as the bypass
capacitance increases due to the RC time constant at
the bypass pin that is created by the internal 250-k
resistor and external capacitor.
A typical application circuit is shown in Figure 22.
Figure 22. Typical Application Circuit
Solder pad footprint recommendations for the devices
are presented in an application bulletin
Solder Pad
Recommendations for Surface-Mount Devices
, litera-
ture number AB-132, available for download from the
TI web site (www.ti.com).
Like most low dropout regulators, the TPS796xx
requires an output capacitor connected between OUT
and GND to stabilize the internal control loop. The
minimum recommended capacitance is 1 μF. Any
1 μF or larger ceramic capacitor is suitable.
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS796xx has an NR
pin which is connected to the voltage reference
through a 250-k
internal resistor. The 250-k
internal resistor, in conjunction with an external by-
pass capacitor connected to the NR pin, creates a
low-pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. In
order for the regulator to operate properly, the current
flow out of the NR pin must be at a minimum,
because any leakage current creates an IR drop
across the internal resistor, thus creating an output
error. Therefore, the bypass capacitor must have
minimal
leakage
current.
should be no more than 0.1-μF in order to ensure that
it is fully charged during the quickstart time provided
by the internal switch shown in the functional block
diagram.
where:
V
REF
= 1.2246 V typ (the internal reference
voltage)
Resistors R1 and R2 should be chosen for approxi-
mately 40-μA divider current. Lower value resistors
can be used for improved noise performance, but the
device wastes more power. Higher values should be
avoided, as leakage current at FB increases the
output voltage error.
The
bypass
capacitor
9