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參數(shù)資料
| 型號(hào)： | TMX320C6413ZTSA400 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 58/140頁(yè) |
| 文件大?。?/td> | 1958K |
| 代理商： | TMX320C6413ZTSA400 |
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Terminal Functions
58
April 2004
Revised May 2005
SPRS247E
Table 3
9. Terminal Functions (Continued)
NAME
DESCRIPTION
IPD/
IPU
TYPE
NO.
EMIFA (32-BIT)
CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
H19
O/Z
IPU
N20
O/Z
IPU
R20
O/Z
IPU
F20
O/Z
IPU
AB21
O/Z
IPU
EMIFA byte-enable control
P21
O/Z
IPU
A22
O/Z
IPU
D16
O/Z
IPU
Can be directly connected to SDRAM read and write mask signal (SDQM)
T19
O/Z
IPU
EMIFA peripheral data transfer, allows direct transfer between external peripherals
EMIFA (32-BIT)
BUS ARBITRATION
J21
O
IPU
EMIFA hold-request-acknowledge to the host
J22
I
IPU
EMIFA hold request from the host
R19
O
IPU
EMIFA bus request output
EMIFA (32-BIT)
ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6
clock) is selected at reset via the pullup/pulldown resistors on the AEA[20:19] pins.
AECLKIN is the default for the EMIFA input clock.
ACE3
ACE2
ACE1
ACE0
ABE3
ABE2
ABE1
ABE0
APDT
EMIFA memory space enables
Enabled by bits 28 through 31 of the word address
Only one pin is asserted during any external data access
EMIFA byte enable control
Decoded from the low-order address bits. The number of address bits or byte
enables used depends on the width of external memory.
Byte-write enables for most types of memory
AHOLDA
AHOLD
ABUSREQ
AECLKIN
K22
I
IPD
AECLKOUT2
U22
O/Z
IPD
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock,
or CPU/6 clock) frequency divided-by-1, -2, or -4.
AECLKOUT1
F22
O/Z
IPD
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
AARE/
ASDCAS/
ASADS/ASRE
D20
O/Z
IPU
EMIFA asynchronous memory read-enable/SDRAM column-address
strobe/programmable synchronous interface-address strobe or read-enable
For programmable synchronous interface, the RENEN field in the CE Space
Secondary Control Register (CExSEC) selects between ASADS and ASRE:
If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal.
If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.
AAOE/
ASDRAS/
ASOE
E20
O/Z
IPU
EMIFA asynchronous memory output-enable/SDRAM row-address
strobe/programmable synchronous interface output-enable
AAWE/
ASDWE/
ASWE
C20
O/Z
IPU
EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable
synchronous interface write-enable
ASDCKE
K21
O/Z
IPU
EMIFA SDRAM clock-enable (used for self-refresh mode).
If SDRAM is not in system, ASDCKE can be used as a general-purpose output.
ASOE3
AARDY
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
P19
L21
O/Z
I
IPU
IPU
EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface)
Asynchronous memory ready input
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