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參數(shù)資料
| 型號： | TMS664414DGE-8 |
| 英文描述： | SDRAM|4X4MX4|CMOS|TSOP|54PIN|PLASTIC |
| 中文描述： | 內(nèi)存| 4X4MX4 |的CMOS |的TSOP | 54PIN |塑料 |
| 文件頁數(shù)： | 8/56頁 |
| 文件大?。?/td> | 958K |
| 代理商： | TMS664414DGE-8 |
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TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
operation (continued)
Table 3. Data/Output Mask Enable (DQM) Command Truth Table
COMMAND
STATE OF BANK(S)
DQM
(DQML/DQMU)§
(n)
D0–D3 (x4)
D0–D7 (x8)
D0–D15 (x16)
(n)
N/A
Q0–Q3 (x4)
Q0–Q7 (x8)
Q0–Q15 (x16)
(n+2)
Hi-Z
MNEMONIC
—
Any bank = deac
X
—
—
Any bank = actv
(no access operation)
X
N/A
Hi-Z
—
Data-in enable
Any bank = write
L
V
N/A
ENBL
Data-in mask
Any bank = write
H
M
N/A
MASK
Data-out enable
Any bank = read
L
N/A
V
ENBL
Data-out mask
For execution of these commands on cycle n, one of the following must be true:
— CKE (n–1) must be high
— tCESP from power-down exit (PDE)
— nCLE from clock-suspend (HOLD) exit
— tCESP and tRC from self-refresh (SLFR) exit
CS (n), RAS (n), CAS (n), W (n), and A0–A13 (n) are don’t care entries.
§DQM is used for x4/x8 (no byte control). DQM (n) operations correspond to D0–D7 and Q0–Q7 events. DQML/DQMU are used for x16 (for
byte-control). DQML (n) operations correspond to D0–D7 and Q0–Q7 events, while DQMU (n) operations correspond to D8–D15 and Q8–Q15
events.
A bank is no longer in an access operation one cycle after the last data-out cycle of a READ (READ-P) operation, and two cycles after the last
data-in cycle of a WRT (WRT-P) operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in
cycle of a WRT (WRT-P) operation.
Legend:
Any bank = read
H
N/A
Hi-Z
MASK
n
=
CLK cycle number
actv
=
Activated
L
=
Logic low
deac
=
Deactivated
H
=
Logic high
write
=
Activated and accepting data in on cycle n
X
=
Don’t care (either logic high or logic low)
read
=
Activated and delivering data out on cycle n + 2
V
=
Valid
M
=
Masked input data
N/A
=
Not applicable
Hi-Z
=
High impedance
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| TMS664814DGE-10 | SDRAM|4X2MX8|CMOS|TSOP|54PIN|PLASTIC |
| TMS664814DGE-8 | SDRAM|4X2MX8|CMOS|TSOP|54PIN|PLASTIC |
| TMS664814DGE-8A | SDRAM|4X2MX8|CMOS|TSOP|54PIN|PLASTIC |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS664414DGE-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X4MX4|CMOS|TSOP|54PIN|PLASTIC |
| TMS664814 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS66481410 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS6648148 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS6648148A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
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