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參數(shù)資料
| 型號： | TMS57535A |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 480-Channel Source Driver for TFT liquid-crystal display (LCD) |
| 中文描述： | 480通道的TFT液晶源驅(qū)動器，液晶顯示器（LCD） |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 192K |
| 代理商： | TMS57535A |
TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142
–
AUGUST 2001
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
cascade
Multiple chips can be used in a cascade connection.
Input EIO pad at lead (head) chip is fixed to H.
Input EIO after secondary chips are connected to output EIO of lead chip.
Receiving the display data
The lead (head) chip is set to
control signal input mode
(also called
control mode
), and the receivers at
LV0+,
–
and CLK+,
–
on all chips are activated by the rising edge of TP1.
Input the reset (RST) signal to LV0+,
–
as L. This RST must be maintained over 200 ns after rising of TP1.
Input RST as H to LV0+,
–
. The duration of H must be over 50 ns and at least three CLK cycles.
Input the RST as L to LV0+,
–
; then change to the
data input mode
function. Input TP1 again when a second
RST is necessary.
Data sampling starts at the rising edge of CLK after reading of RST=L.
The internal counter starts counting the data cycle for EIO signal generation at the same time data sampling
starts.
When data sampling is finished, the receivers turn off.
After the receivers turn off, keep the timing for at least five more CLK cycles until TP1 is applied.
Figure 1 shows the rough timing chart from application of TP1 to the start of data sampling.
DATA1
DATA2
DATA1
DATA2
Read Reset (RST)
Read RST = L
Start Data Sampling
RST
Greater than 50 ns
and 3 CLK Cycles
200 ns
Control Signal Input Mode
Input EIO
H
TP1
LV1+ to LV4+
LV0+
CLK+
Data Input Mode
CLK1
Figure 1. Timing From Start to Sampling (Reference)
P
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