
TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142
–
AUGUST 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
CLKA, CLKB
I
Clock (mini-LVDS). Shift clock (refer to Table 1)
LV0A, B
–
LV5A, B
I
Display data (mini-LVDS). Displays data with gray-scale data (6-bit) and control signal (RST=reset) (refer to Table
1)
L/R
I
Shift direction. Controls the direction of loaded data at the shift register (refer to Table 2)
EIO1, EIO2
I/O
Start pulse. Input/Output definition of address shift register (refer to Table 2)
TP1
I
Input mode and output timing control. Changes the input mode, latches the registered data, and transfers to the DAC
at the rising edge. Voltage to LCD pixel is output at falling edge.
POL
I
Polarity control. Controls the polarity of the output. Defined by the POL signal at TP1 as H
(refer to Table 3)
LCH
I
Drivability control.
LCH = H: Higher drivability for heavy load
LCH = L; Normal drivability
LP
I
Low power mode selection. Decreases the charge/discharge current to output load. LP=H: low power mode. Refer
to the application notes.
SB
I
Bus-line set-back. Changes the data order of mini-LVDS input (see Table 1)
OUT1
–
OUT480
O
Output. Supplies voltage to each LCD pixel.
VDD1, VSS1
I
Power supply (output circuits). Power supply for output (driving) circuits
VDD2(*1)
VDD2(*2)
VSS2
VSS*
I
Power supply (control=logic circuits). VDD2(*1) is for mini-LVDS receiver and VDD2(*2) is for other logic circuits.
Supplies stable voltage to VDD2(*1).
VDD2(*1) and VDD2(*2) must be at the same electric potential.
Possible to wire the VSS potential between each mini-LVDS signal line from VSS* terminal, though no wiring, no
relation to function itself.
GMA1
–
GMA10
I
γ
-corrected power supplies. Receives the external
γ
-corrected power supplies by using operational amplifiers.
Maintain the recommended operating conditions.
Table 1. Function Table (Bus-Line Set-Back)
PIN NAME
SB=L
SB=H
LV0A
DUMMY
LV4
–
LV0B
DUMMY
LV4+
LV1A
LV0+
LV3
–
LV1B
LV0
–
LV3+
LV2A
LV1+
LV2
–
LV2B
LV1
–
LV2+
CLKA
CLK+
CLK
–
CLKB
CLK
–
CLK+
LV3A
LV2+
LV1
–
LV3B
LV2
–
LV1+
LV4A
LV3+
LV0
–
LV4B
LV3
–
LV0+
LV5A
LV4+
DUMMY
LV5B
LV4
–
DUMMY
Suffix + indicates positive potential and
–
indicates negative potential
at each differential signal input pair.
P