參數(shù)資料
型號(hào)： TMS370CX0X
廠商： Texas Instruments, Inc.
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁(yè)數(shù)： 12/54頁(yè)
文件大?。?/td> 785K
代理商： TMS370CX0X
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
system reset (continued)
Table 6. Reset Sources
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Once a reset is activated, the following sequence of events occurs:
1.
The CPU registers are initialized: ST = 00h, SP = 01h (reset state).
2.
Registers A and B are initialized to 00h (no other RAM is changed).
3.
The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
4.
The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
5.
Program execution begins with an opcode fetch from the address pointed to by the PC.
The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode
fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control
register bits are initialized to their reset state.
interrupts
The TMS370 family software programmable interrupt structure permits flexible on-chip and external-interrupt
configurations to meet real-time interrupt-driven application requirements. The hardware-interrupt structure
incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt
level 2. The two priority levels can be masked independently by the global-interrupt mask bits (IE1 and IE2) of
the status register.
Each system interrupt is configured independently to either the high- or low-priority chain by the application
program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of
the system interrupt. However, since each system interrupt is configured selectively on either the high- or
low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.
Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority
chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending
interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and
priority conditions.
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