參數(shù)資料
型號： TMS370C732A
廠商： Texas Instruments, Inc.
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁數(shù)： 14/54頁
文件大?。?/td> 785K
代理商： TMS370C732A
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupts (continued)
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Relative priority within an interrupt level.
Releases microcontroller from STANDBY and HALT low-power modes.
§Releases microcontroller from STANDBY low-power mode.
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INTERRUPT SOURCE
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Watchdog overflow
Oscillator fault detect
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INTERRUPT FLAG
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WD OVRFL INT FLAG
OSC FLT FLAG
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RESET
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SYSTEM
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7FFEh, 7FFFh
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VECTOR
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PRIORITY
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1
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Timer 1 input capture 1
Watchdog overflow
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Timer 1 compare 2
T1IC1 INT FLAG
WD OVRFL INT FLAG
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T1 OVRFL INT FLAG
T1C1 INT FLAG
T1C2 INT FLAG
T1EDGE INT FLAG
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privileged operation and EEPROM write-protection override
The TMS370Cx9x family has significant flexibility to enable the designer to software-configure the system and
peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation
ensures the integrity of the system configuration, once it is defined for an application. Following a hardware
reset, the TMS370Cx9x operates in the privileged mode, where all peripheral file registers have unrestricted
read/write access, and the application program configures the system during the initialization sequence
following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set
to one to enter the nonprivileged mode; disabling write operations to specific configuration control bits within
the peripheral file. Table 8 displays the system configuration bits that are write-protected during the
nonprivileged mode and must be configured by software prior to exiting the privileged mode.
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The privilege bits are shown in a
bold typeface in the system configuration
registers section.
REGISTER
P010.6
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P011.2
P011.4
SCCRO
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MEMORY DISABLE
AUTOWAIT DISABLE
OSC POWER
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PF AUTO WAIT
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T1PRI
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P012.6
P012.7
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P012.3
PWRDWN/IDLE
HALT/STANDBY
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PRIVILEGE DISABLE
INT1 NMI
CPU STEST
BUS STEST
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P07F.6
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AD PRIORITY
P04F.6
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T1 PRIORITY
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ADPRI
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