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| 型號(hào)： | TMS370C352A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 13/54頁 |
| 文件大?。?/td> | 785K |
| 代理商： | TMS370C352A |
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TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupts (continued)
TIMER 1
CPU
NMI
Logic
Enable
IE1
IE2
Level 1 INT
Level 2 INT
T1 PRI
Priority
Overflow
Compare1
Ext Edge
Compare2
Input Capture 1
STATUS REG
EXT INT1
INT1 PRI
INT1
Watchdog
AD INT
AD PRI
A/D
Figure 4. Interrupt Control
The TMS370Cx9x has three hardware system interrupts (plus RESET) as shown in Table 7. Each system
interrupt has a dedicated vector located in program memory through which control is passed to the interrupt
service routines. A system interrupt can have multiple interrupt sources. All of the interrupt sources are
individually maskable by local interrupt-enable control bits in the associated PF. Each interrupt source FLAG
bit is individually readable for software polling or for determining which interrupt source generated the
associated system interrupt.
Two of the system interrupts are generated by on-chip peripheral functions, and one external interrupt is
supported. Software configuration of the external interrupt is performed through the INT1 control registers in
peripheral file frame 1. The external is software-configurable for input polarity (rising or falling edge) for ease
of system interface. External interrupt INT1 is software-configurable as either a maskable or non-maskable
interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual or global enable
mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should be configured
during the initialization sequence following reset. To maximize pin flexibility, external interrupt INT1 can be
software-configured as a general-purpose input pin if the interrupt function is not required.
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