
SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240x Pin List and Package Options
(Continued)
PIN NAME
LF2407
LF2406
LF2402
DESCRIPTION
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS (CONTINUED)
PLLF
11
9
38
Filter input 1
PLLF2
10
8
37
Filter input 2
VCCP (5V)
58
40
60
Flash programming voltage pin. This pin must be connected to a 5-V supply for
Flash programming. The Flash cannot be programmed if this pin is connected
to GND. When not programming the Flash (i.e., during normal device
operation), this pin can either be left connected to the 5-V supply or it can be tied
to GND. This pin must not be left floating at any time. Do not use any
current-limiting resistor in series with the 5-V supply on this pin. This pin is a “no
connect” (NC) on ROM parts and can be left open.
TP1 (Flash)
60
42
61
Flash array test pin.
Do not connect.
TP2 (Flash)
63
44
62
Flash array test pin
. Do not connect.
BIO
/IOPC1
119
85
Branch control input. BIO is polled by the
BCND pma,BIO
instruction. If BIO is
low, a branch is executed. If BIO is not used, it should be pulled high. This pin
is configured as a branch control input by all device resets. It can be used as
a GPIO, if not used as a branch control input.
(
↑
)
EMULATION AND TEST
EMU0
90
61
7
Emulator I/O #0 with internal pullup. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is defined as input/output
through the JTAG scan.
(
↑
)
Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high,
EMU1/OFF is used as an interrupt to or from the emulator system and is defined
as an input/output through the JTAG scan. When TRST is driven low, this pin
is configured as OFF. EMU1/OFF, when active low, puts all output drivers in the
high-impedance state. Note that OFF is used exclusively for testing and
emulation purposes (not for multiprocessing applications). Therefore, for the
OFF condition, the following apply:
TRST = 0
EMU0 = 1
EMU1/OFF = 0
(
↑
)
(
↑
)
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.
EMU1/OFF
91
62
8
TCK
135
94
29
JTAG test clock with internal pullup
TDI
139
96
30
(
↑
)
TDO
142
99
31
JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) is shifted out of TDO on the falling edge of TCK.
(
↓
)
TMS
144
100
32
JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
(
↑
)
TMS2
36
25
48
JTAG test-mode select 2 (TMS2) with internal pullup. This serial control input
is clocked into the TAP controller on the rising edge of TCK. Used for test and
emulation only. This pin can be left unconnected in user applications. If the PLL
bypass mode is desired, TMS2, TMS, and TRST should be held low during
reset.
(
↑
)
Bold, italicized pin names
indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
Internal pullup
↓
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)