參數(shù)資料
型號(hào): TMS29F800T-80CDCDQ
廠商: Texas Instruments, Inc.
英文描述: 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES
中文描述: 1048576 8位/ 524288由16位閃存
文件頁數(shù): 14/51頁
文件大小: 685K
代理商: TMS29F800T-80CDCDQ
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
read/reset command
The read or reset mode is activated by writing either of the two read/reset command sequences into the
command register. The device remains in this mode until another valid command sequence is input in the
command register. Memory data is available in the read mode and can be read with standard microprocessor
read-cycle timing.
On power up, the device defaults to the read/reset mode. A read/reset command sequence is not required and
memory data is available.
algorithm-selection command
The algorithm-selection command allows access to a binary code that matches the device with the proper
programming and erase command operations. After writing the three-bus-cycle command sequence, the first
byte of the algorithm-selection code can be read from address XX00h. The second byte of the code can be read
from address XX01h (see Table 6). This mode remains in effect until another valid command sequence is written
to the device.
program command
Programming is a four-bus-cycle command sequence. The first three bus cycles put the device into the
program-setup state. The fourth bus cycle loads the address location and the data to be programmed into the
device. The addresses are latched on the falling edge of WE while the data is latched on the rising edge of WE
in the fourth bus cycle. The rising edge of WE starts the program operation. The embedded programming
function automatically provides needed voltage and timing to program and verify the cell margin. Any further
commands written to the device during the program operation are ignored.
Programming can be performed at any address location in any sequence. When erased, all bits are in a
logic-high state. Logic lows are programmed into the device. Only an erase operation can change bits from logic
lows to logic highs. Attempting to program a 1 into a bit that has been programmed previously to a 0 causes
the internal-pulse counter to exceed the pulse-count limit, which sets the exceed-time-limit indicator (DQ5) to
a logic-high state. The automatic-programming operation is complete when the data on DQ7 is equivalent to
the data written to bit DQ5, at which time the device returns to the read mode and addresses are no longer
latched. Figure 9 shows a flowchart of the typical device-programming operation.
chip-erase command
Chip erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup
state. The next two bus cycles unlock the erase mode. The sixth bus cycle loads the chip-erase command. This
command sequence is required to ensure that the memory contents are not erased accidentally. The rising edge
of WE starts the chip-erase operation. Any further commands written to the device during the chip-erase
operation are ignored.
The embedded chip-erase function automatically provides voltage and timing needed to program and to verify
all the memory cells prior to electrical erase. It then erases and verifies the cell margin automatically without
programming the memory cells prior to erase.
Figure 12 shows a flowchart of the typical chip-erase operation.
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PDF描述
TMS29F800B-80CDCDQ 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES
TMS29F800T-90CDCDE 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES
TMS29F800B-90CDCDE 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES
TMS29F800T-90CDCDL 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES
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