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參數(shù)資料
| 型號： | TMS29F800B-80CDCDQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES |
| 中文描述： | 1048576 8位/ 524288由16位閃存 |
| 文件頁數(shù)： | 12/51頁 |
| 文件大?。?/td> | 685K |
| 代理商： | TMS29F800B-80CDCDQ |
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TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
erasure and programming
Erasure and programming of the ’29F800 are accomplished by writing a sequence of commands using standard
microprocessor write timing. The commands are written to a command register and input to the command-state
machine (CSM). The CSM interprets the command entered and initiates program, erase, suspend, and resume
operations as instructed. The
CSM acts as the interface between the write-state machine (WSM) and
external-chip operations. The WSM controls all voltage generation, pulse generation, preconditioning, and
verification of memory contents. Program and block-/chip-erase functions are fully automatic. Once the end of
a program or erase operation has been reached, the device resets internally to the read mode. If V
CC
drops
below the low-voltage-detect level (V
LKO
), any programming or erase operation is aborted and subsequent
writes are ignored until the V
CC
level is greater than V
LKO
. The control pins must be logically correct to prevent
unintentional command writes or programming or erasing.
command definitions
Device operating modes are selected by writing specific address and data sequences into the command
register. Table 6 defines the valid command sequences. Writing incorrect address and data values or writing
them in the incorrect sequence causes the device to reset to the read mode. The command register does not
occupy an addressable memory location. The register is used to store the command sequence, along with the
address and data needed by the memory array. Commands are written by setting CE = V
IL
, OE = V
IH
, and
bringing WE from logic high to logic low. Addresses are latched on the falling edge of WE and data is latched
on the rising edge of WE. Holding WE = V
IL
and toggling CE is an alternative method. See the switching
characteristics of the write/erase/program-operations section for specific timing information.
P
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| TMS29F800B-90CDCDE | 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES |
| TMS29F800T-90CDCDL | 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES |
| TMS29F800B-90CDCDL | 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES |
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