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參數資料
| 型號： | TMS29F800B-120CDCDL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES |
| 中文描述： | 1048576 8位/ 524288由16位閃存 |
| 文件頁數： | 16/51頁 |
| 文件大小： | 685K |
| 代理商： | TMS29F800B-120CDCDL |
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TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
erase-resume command
The erase-resume command (30h) restarts a suspended sector-erase operation from the point where it was
halted. Erase resume is a one-bus-cycle command. The addresses can be V
IL
or V
IH
and the erase-resume
command (30h) is latched on the rising edge of WE. When an erase-suspend/erase-resume command
combination is written, the internal-pulse counter (exceed timing limit) is reset. The erase-resume command
is valid only in the erase-suspend state. After the erase-resume command is executed, the device returns to
the valid sector-erase state and further writes of the erase-resume command are ignored. After the device has
resumed the sector-erase operation, another erase-suspend command can be issued to the device.
operation status
The status of the device during an automatic-programming algorithm, chip-erase, or automatic-erase algorithm
can be determined in three ways:
DQ7: Data polling
DQ6: Toggle bit
RY/BY: Ready/busy bit
status-bit definitions
During operation of the automatic embedded program and erase functions, the status of the device can be
determined by reading the data state of designated outputs. The data-polling bit (DQ7) and toggle bit (DQ6)
require multiple successive reads to observe a change in the state of the designated output. Table 7 defines
the values of the status flags.
P
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