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參數(shù)資料
| 型號： | TMS28F010A-10C4DUL4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY |
| 中文描述： | 1048576位閃存電可擦除可編程只讀存儲器 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 328K |
| 代理商： | TMS28F010A-10C4DUL4 |
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Table 1. Operation Modes
FUNCTION
MODE
VPP
(1)
VPPL
VPPL
VPPL
E
(22)
G
(24)
A0
(12)
A9
(26)
W
(31)
DQ0–DQ7
(13–15, 17–21)
Read
VIL
VIL
VIH
VIL
VIH
X
X
X
VIH
VIH
X
Data Out
Output Disable
X
X
HI-Z
Read
Standby and Write Inhibit
X
X
HI-Z
Algorithm Selection Mode
Algorithm-Selection Mode
VPPL
VIL
VIL
VIL
VIH
X
VID
VIH
Mfr Equivalent Code 89h
Device Equivalent Code B4h
Read
VPPH
VPPH
VPPH
VPPH
VIL
VIL
VIH
VIL
VIL
VIH
X
VIH
X
VIH
VIH
X
Data Out
Read/
Write
Output Disable
X
X
HI-Z
Standby and Write Inhibit
Write
X
X
X
X
HI-Z
Data In
VIL
NOTE: X can be VIL or VIH.
VPPL
≤
VCC + 2 V; VPPH is the programming voltage specified for the device. For more details, refer to the recommended operating conditions.
operation
read/output disable
When the outputs of two or more TMS28F010As are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of other devices. To
read the output of the TMS28F010A, a low-level signal is applied to the E and G pins. All other devices in the
circuit should have their outputs disabled by applying a high-level signal to one of these pins.
standby and write inhibit
Active I
CC
current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100
μ
A with a
high CMOS level on E. In this mode, all outputs are in the high-impedance state. The TMS28F010A draws active
current when it is deselected during programming, erasure, or program/erase verification. It continues to draw
active current until the operation is terminated.
algorithm-selection mode
The algorithm-selection mode provides access to a binary code identifying the correct programming and erase
agorithms. This mode is activated when A9 (pin 26) is forced to V
ID
. Two identifier bytes are accessed by toggling
A0. All other addresses must be held low. A0 low selects the manufacturer equivalent code 89h, and A0 high
selects the device equivalent code B4h, as shown in the algorithm-selection mode table below:
IDENTIFIER
PINS
A0
VIL
VIH
DQ7
1
DQ6
0
DQ5
0
DQ4
0
DQ3
1
DQ2
0
DQ1
0
DQ0
1
HEX
89
Manufacturer Equivalent Code
Device Equivalent Code
1
0
1
1
0
1
0
0
B4
NOTE: E = G = VIL, A1–A8 = VIL, A9 = VID, A10–A16 = VIL, VPP = VPPL.
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic 0. Afterwards, the entire chip is erased. At this point, the bits, now logic 1s, can be programmed
accordingly. Refer to the Fastwrite and Fasterase algorithms for further detail.
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