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| 型號(hào)： | TMS27C512-120JL4 |
| 英文描述： | x8 EPROM |
| 中文描述： | x8存儲(chǔ)器 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 184K |
| 代理商： | TMS27C512-120JL4 |
TMS27C512 65536 BY 8-BIT UV ERASABLE
TMS27PC512 65536 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
switching characteristics over recommended ranges of operating conditions
PARAMETER
TEST CONDITIONS
(SEE NOTES 3 AND 4)
’27C512-10
’27PC512-10
’27C512-12
’27PC512-12
UNIT
MIN
MAX
100
MIN
MAX
120
ta(A)
ta(E)
ten(G)
tdis
Access time from address
ns
Access time from chip enable
CL= 100 pF,
CL = 100 F,
1 Series 74 TTL Load,
Input tr
≤
20 ns,
Input tf
≤
20 ns
100
120
ns
Output enable time from G/VPP
Output disable time from G/VPP or E, whichever occurs first
Output data valid time after change of address, E, or G/VPP,
whichever occurs first
55
55
ns
0
45
0
45
ns
tv(A)
0
0
ns
PARAMETER
TEST CONDITIONS
(SEE NOTES 3 AND 4)
’27C512-15
’27PC512-15
UNIT
MIN
MAX
150
ta(A)
ta(E)
ten(G)
tdis
Access time from address
ns
Access time from chip enable
CL= 100 pF,
CL = 100 F,
1 Series 74 TTL Load,
Input tr
≤
20 ns,
Input tf
≤
20 ns
150
ns
Output enable time from G/VPP
Output disable time from G/VPP or E, whichever occurs first
Output data valid time after change of address, E, or G/VPP, whichever
occurs first
75
ns
0
60
ns
tv(A)
0
ns
PARAMETER
TEST CONDITIONS
(SEE NOTES 3 AND 4)
’27C512-20
’27PC512-20
’27C512-25
’27PC512-25
UNIT
MIN
MAX
200
MIN
MAX
250
ta(A)
ta(E)
ten(G)
tdis
Access time from address
ns
Access time from chip enable
CL= 100 pF,
CL = 100 F,
1 Series 74 TTL Load,
Input tr
≤
20 ns,
Input tf
≤
20 ns
200
250
ns
Output enable time from G/VPP
Output disable time from G/VPP or E, whichever occurs first
Output data valid time after change of address, E, or G/VPP,
whichever occurs first
Value calculated from 0.5 V delta to measured output level. This parameter is only sampled.
NOTES:
3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (see Figure 2).
4. Common test conditions apply for tdis except during programming.
75
100
ns
0
60
0
60
ns
tv(A)
0
0
ns
switching characteristics for programming: V
CC
= 6.50 V and G/V
PP
= 13 V (SNAP! Pulse),
T
A
= 25
°
C (see Note 3)
PARAMETER
MIN
MAX
UNIT
tdis(G)
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low.
Disable time, output from G/VPP
0
130
ns
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|---|---|
| TMS27C512-12JE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS27PC512 65536 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES |
| TMS27C512-12JE4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| TMS27C512-12JL | 制造商:Texas Instruments 功能描述: |
| TMS27C512-12JL4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| TMS27C512-150JE4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
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