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| 型號： | TMS27C512-120JL4 |
| 英文描述： | x8 EPROM |
| 中文描述： | x8存儲器 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 184K |
| 代理商： | TMS27C512-120JL4 |
TMS27C512 65536 BY 8-BIT UV ERASABLE
TMS27PC512 65536 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
operation
The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are
TTL level except for V
PP
during programming (13 V for SNAP! Pulse) and 12 V on A9 for signature mode.
Table 2. Operation Modes
MODE
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
E
VIL
VIL
VCC
X
VIL
VIH
VCC
X
VIH
X
VIL
VPP
VCC
X
VIL
VIL
VCC
X
VIH
VPP
VCC
X
VIL
VIL
VCC
G/VPP
VCC
A9
VCC
X
VH
VIL
VH
VIH
A0
X
X
X
X
X
X
CODE
DQ0–DQ7
Data Out
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
MFG
97
DEVICE
85
X can be VIL or VIH.
VH = 12 V
±
0.5 V.
read/output disable
When the outputs of two or more TMS27C512s or TMS27PC512s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G/V
PP
pins.
All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.
latchup immunity
Latchup immunity on the TMS27C512 and TMS27PC512 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active I
CC
supply current can be reduced from 30 mA to 500
μ
A (TTL-level inputs) or 250
μ
A (CMOS-level
inputs) by applying a high TTL/CMOS signal to the E pin. In this mode all outputs are in the high-impedance
state.
erasure (TMS27C512)
Before programming, the TMS27C512 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 angstroms). EPROM erasure before programming is
necessary to assure that all bits are in the logic high state. Logic lows are programmed into the desired locations.
A programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose
(UV intensity
×
exposure time) is 15-W
s/cm
2
. A typical 12-mW/cm
2
, filterless UV lamp erases the device in
21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that
normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C512, the
window should be covered with an opaque label.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TMS27C512-12JE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS27PC512 65536 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES |
| TMS27C512-12JE4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| TMS27C512-12JL | 制造商:Texas Instruments 功能描述: |
| TMS27C512-12JL4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| TMS27C512-150JE4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
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