- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382638 > TMP320LF2402APGES (Texas Instruments, Inc.) DSP CONTROLLERS PDF資料下載
參數(shù)資料
| 型號(hào)： | TMP320LF2402APGES |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSP CONTROLLERS |
| 中文描述： | DSP控制器 |
| 文件頁(yè)數(shù)： | 17/134頁(yè) |
| 文件大?。?/td> | 1759K |
| 代理商： | TMP320LF2402APGES |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K
JULY 2000
REVISED AUGUST 2005
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options
(Continued)
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS
DS
87
Data space strobe. IS, DS, and PS are always
high unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state.
IS
82
I/O space strobe. IS, DS, and PS are always high
unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state.
PS
84
Program space strobe. IS, DS, and PS are always
high unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state.
R/W
92
Read/write qualifier signal. R/W indicates transfer
direction during communication to an external
device. It is normally in read mode (high), unless
low level is asserted for performing a write
operation. R/W is placed in the high-impedance
state.
W/R
/ IOPC0
W/R
19
Write/Read qualifier or GPIO. This is an inverted
R/W signal useful for zero-wait-state memory
interface. It is normally low, unless a memory write
operation is performed.
See Table 12, Port C
section, for reset note regarding LF2406A and
LF2402A.
(
↑
)
Read-enable strobe. Read-select indicates an
active, external read cycle. RD is active on all
external program, data, and I/O reads. RD is
placed in the high-impedance state.
IOPC0
19
14
14
RD
93
WE
89
Write-enable strobe. The falling edge of WE
indicates that the device is driving the external
data bus (D15
D0). WE is active on all external
program, data, and I/O writes. WE is placed in the
high-impedance state.
STRB
96
External memory access strobe. STRB is always
high unless asserted low to indicate an external
bus cycle. STRB is active for all off-chip
accesses. STRB is placed in the high-impedance
state.
Bold, italicized pin names
indicate pin function after reset.
GPIO
General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
CCA
be isolated from the digital supply voltage (and V
SSA
from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (V
DD
, V
DDO
, V
SS
, or V
SSO
) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
Internal pullup
↓
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMP320LF2402APZA | DSP CONTROLLERS |
| TMP320LF2402APZS | DSP CONTROLLERS |
| TMP320LF2402AVFA | DSP CONTROLLERS |
| TMP320LF2402AVFS | DSP CONTROLLERS |
| TMP320LF2403APGA | DSP CONTROLLERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP320LF2402APGS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|64PIN|PLASTIC |
| TMP320LF2402APZA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMP320LF2402APZS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMP320LF2402AVFA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMP320LF2402AVFS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。