
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
65
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 42)
NO.
200
UNIT
MIN
35
11
MAX
1
3
4
t
c(TCK)
t
su(TDIV-TCKH)
t
h(TCKH-TDIV)
Cycle time, TCK
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
ns
ns
ns
9
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 42)
NO.
PARAMETER
200
UNIT
MIN
4.5
MAX
2
t
d(TCKL-TDOV)
Delay time, TCK low to TDO valid
12
ns
TCK
TDO
TDI/TMS/TRST
1
2
3
4
2
Figure 42. JTAG Test-Port Timing