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| 型號： | ISL6112INZA-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/30頁 |
| 文件大小： | 938K |
| 描述： | IC PWR CNTRLR DUAL SLT 48-TQFP |
| 標準包裝： | 1,000 |
| 類型： | 熱交換控制器 |
| 應用： | 通用型，PCI Express? |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 3.3V，12V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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ISL6112
17
FN6456.1
August 25, 2011
both the MAIN and AUX outputs. A fault condition can
alternatively be cleared under SMI control of the ENABLE bits in
the CNTRL registers (see Control Register Bits D[1:0] on
page21). When the circuit protection trips, FAULT
is asserted if
the outputs were enabled through the HPI inputs. If SMI is
enabled, INT
is asserted (unless interrupts are masked). Note
that INT
is deasserted by writing a Logic 1 back into the
respective fault bit positions in the STAT register or the Common
Status Register (CS) 8-Bits, Read/Write on page24.
The ISL6112 current regulation duration (t
FILTER
) is individually
set for each slot by an external capacitor at the CFILTER pin to
GND. Once the CR mode is entered, the external cap is charged
with a 2.5礎(chǔ) current source to 1.25V. Once this threshold has
been reached, the IC turns off only the related faulted outputs
[either both MAIN (external FETs) outputs or AUX (internal FET)]
and sets the FAULT
output low. For a desired t
FILTER
, the value for
C
FILTER
is given by Equation 4:
where 500k?is the nominal V
FILTER/nominal
I
FILTER
and where
t
FILTER
is the desired response time, with the values for I
FILTER
and V
FILTER
being found in the Electrical Specifications Table
on page7. See Table 2 for nominal t
FILTER
times for given
C
FILTER
cap values.
Because the ISL6112 has its CR feature invoked as it turns on the
FETs into the load, t
FILTER
consideration is minimal. A maximum
bulk capacitance is specified for each supported power level, and it
must be charged at the CR limit. In-rush current time must be
considered when determining t
FILTER
duration.
Power-Down Cycle
When a slot is turned off under either HPI or SMI control, internal
discharge FETs connected to the output load provide a discharge
path for load capacitance connected to the parts outputs. These
FETs ensure the outputs are pulled to GND. This is a compliance
requirement if a replacement add-in card is inserted into the slot.
Thermal Shutdown
The internal VAUX MOSFETs are protected against damage not
only by current limiting, but by a dual-mode over-temperature
protection scheme as well. Each slot controller on the ISL6112 is
thermally isolated from the other. Should an overcurrent
condition raise the junction temperature of one slots controller
and pass elements to +140癈, all outputs for that slot (including
VAUX) are shut off, and the slots FAULT
output is asserted. The
other slots operating condition remains unaffected. However,
should the ISL6112 die temperature exceed +160癈, both slots
(all outputs, including VAUXA and VAUXB) are shut off, whether or
not a current limit condition exists. A +160癈 over-temperature
condition additionally sets the over-temperature bit (OT_INT) in
the Common Status Register (see Common Status Register (CS)
8-Bits, Read/Write on page24).
PWRGD
Outputs
The ISL6112 has two PWRGD
outputs; one for each slot. These
open-drain, active-low outputs require an external pull-up resistor
to V
STBY
. Each output is asserted when a slot has been enabled
and has successfully begun delivering power to its respective
+12V, +3.3V, and VAUX outputs. An equivalent logic diagram for
PWRGD
is shown in Figure 30.
FORCE_ON
Inputs
The level-sensitive, active-low FORCE_ON
inputs are provided to
facilitate design or debugging of systems using the ISL6112.
Asserting FORCE_ON
turns on all three of the respective slots
outputs (12MAIN, 3MAIN, and VAUX), while specifically defeating all
overcurrent and short circuit protections and on-chip thermal
protection for the VAUX supplies. Additionally, asserting FORCE_ON
disables all input and output UVLO protections, with the exception of
the VSTBY input, UVLO.
Asserting FORCE_ON
causes the slot PWRGD
and FAULT
outputs to enter the open-drain state. Additionally, there are
two SMBus accessible register bits (see Control Register Bit
D[2] in Tables 5 and 7) that can be set to disable the
corresponding slots FORCE_ON
pins. This allows system
software to prevent these hardware overrides from being
inadvertently activated during normal use. When not used, each
FORCE_ON
pin can be connected to V
STBY
by using an external
pull-up resistor, or it can simply be shorted to VSTBY.
General Purpose Input (GPI) Pins
Two pins on the ISL6112 are available for use as GPI pins. The logic
state of each of these pins can be determined by polling Bits [4:5] of
the Common Status Register. Both of these inputs are compliant to
3.3V. If GPI is not used, each input must be connected to GND.
Hot-Plug Interface (HPI)
After the input supplies are above their respective UVLO
thresholds, the Hot-Plug Interface can be used for power control
by enabling the control input pins (AUXEN and ON) for each slot.
For the ISL6112 to turn on the VAUX supply for either slot, the
AUXEN control must be enabled after the power-on-reset delay,
t
POR
(typically, 250祍), has elapsed.
System Management Interface (SMI)
The ISL6112 System Management Interface (SMI) uses the
Read_Byte and Write_Byte subsets of the SMBus protocols to
communicate with its host via the SMI bus. The INT
output
signals the controlling processor that one or more events need
attention, if an interrupt-driven architecture is used. Note that the
ISL6112 does not participate in the SMBus Alert Response
Address (ARA) portion of the SMBus protocol.
TABLE 2. NOMINAL t
FILTER
DURATION
C
FILTER
CAPACITANCE (礔)
TIME (ms)
Open
0.01
0.01
5
0.022
11
0.047
24
0.1
50
NOTE: Nominal CR_DUR = C
FILTER
cap (糉) * 500k?
C
FILTER
nominal t
FILTER
500k?/DIV>
------------------------------------------
=
(EQ. 4)
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